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authorWenyou Yang <wenyou.yang@atmel.com>2017-06-02 11:29:04 +0800
committerAnatolij Gustschin <agust@denx.de>2017-06-09 15:33:28 +0200
commit31e5c892b35f1ec90c7b90e6faac79d31145d0e9 (patch)
tree12d18e82f23d25c1dc82962162d3f4f91554d800 /drivers
parentb98efa1db392a21887c0bcd82c013724a11c0d3d (diff)
video: atmel_hlcdfb: Fix misaligned cache operation warning
Fix the warning, ---8<--- CACHE: Misaligned operation at range [3fdffff0, 3fdffffc] ---<8--- Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/atmel_hlcdfb.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index 47078fdaae..f77da2ec97 100644
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -426,7 +426,9 @@ static void atmel_hlcdc_init(struct udevice *dev)
writel(~0UL, &regs->lcdc_baseidr);
/* Setup the DMA descriptor, this descriptor will loop to itself */
- desc = (struct lcd_dma_desc *)(uc_plat->base - 16);
+ desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
+ if (!desc)
+ return;
desc->address = (u32)uc_plat->base;
@@ -436,7 +438,9 @@ static void atmel_hlcdc_init(struct udevice *dev)
desc->next = (u32)desc;
/* Flush the DMA descriptor if we enabled dcache */
- flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
+ flush_dcache_range((u32)desc,
+ ALIGN(((u32)desc + sizeof(*desc)),
+ CONFIG_SYS_CACHELINE_SIZE));
writel(desc->address, &regs->lcdc_baseaddr);
writel(desc->control, &regs->lcdc_basectrl);