Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

6 files changed, 199 insertions, 115 deletions

diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index a7d04b7ea3..223cd5d65c 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -275,5 +275,59 @@ void init_laws(void)
 				law_table[i].size, law_table[i].trgt_id);
 	}
 
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/* check RCW to get which port is used for boot */
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	u32 bootloc = in_be32(&gur->rcwsr[6]);
+	/*
+	 * in SRIO or PCIE boot we need to set specail LAWs for
+	 * SRIO or PCIE interfaces.
+	 */
+	switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
+	case 0x0: /* boot from PCIE1 */
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_PCIE_1);
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_PCIE_1);
+		break;
+	case 0x1: /* boot from PCIE2 */
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_PCIE_2);
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_PCIE_2);
+		break;
+	case 0x2: /* boot from PCIE3 */
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_PCIE_3);
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_PCIE_3);
+		break;
+	case 0x8: /* boot from SRIO1 */
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_RIO_1);
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_RIO_1);
+		break;
+	case 0x9: /* boot from SRIO2 */
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_RIO_2);
+		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+				LAW_SIZE_1M,
+				LAW_TRGT_IF_RIO_2);
+		break;
+	default:
+		break;
+	}
+#endif
+
 	return ;
 }
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 072b178a04..cc57354755 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -36,10 +36,8 @@ COBJS-y += tgec_phy.o
 COBJS-$(CONFIG_P1017)	+= p1023.o
 COBJS-$(CONFIG_P1023)	+= p1023.o
 # The P204x, P304x, and P5020 are the same
-COBJS-$(CONFIG_PPC_P2040) += p5020.o
 COBJS-$(CONFIG_PPC_P2041) += p5020.o
 COBJS-$(CONFIG_PPC_P3041) += p5020.o
-COBJS-$(CONFIG_PPC_P3060) += p3060.o
 COBJS-$(CONFIG_PPC_P4080) += p4080.o
 COBJS-$(CONFIG_PPC_P5020) += p5020.o
 endif
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 953c359e6e..736b8b9582 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = {
 #if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
 	FM_DTSEC_INFO_INITIALIZER(2, 4),
 #endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
+	FM_DTSEC_INFO_INITIALIZER(2, 5),
+#endif
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
 	FM_TGEC_INFO_INITIALIZER(1, 1),
 #endif
@@ -152,6 +155,22 @@ void fm_info_set_phy_address(enum fm_port port, int address)
 }
 
 /*
+ * Returns the PHY address for a given Fman port
+ *
+ * The port must be set via a prior call to fm_info_set_phy_address().
+ * A negative error code is returned if the port is invalid.
+ */
+int fm_info_get_phy_address(enum fm_port port)
+{
+	int i = fm_port_to_index(port);
+
+	if (i == -1)
+		return -1;
+
+	return fm_info[i].phy_addr;
+}
+
+/*
  * Returns the type of the data interface between the given MAC and its PHY.
  * This is typically determined by the RCW.
  */
@@ -181,7 +200,8 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 
 static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
 {
-	int off, ph;
+	int off;
+	uint32_t ph;
 	phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
 	u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
 				CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
@@ -198,12 +218,10 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
 	off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
 
 	/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
-	if (paddr != dtsec1_addr) {
-		/* disable the mac node */
-		fdt_setprop_string(blob, off, "status", "disabled");
-	}
+	if (paddr != dtsec1_addr)
+		fdt_status_disabled(blob, off); /* disable the MAC node */
 
-	/* disable the node point to the mac */
+	/* disable the fsl,dpa-ethernet node that points to the MAC */
 	ph = fdt_get_phandle(blob, off);
 	do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
 		"status", "disabled", strlen("disabled") + 1, 1);
diff --git a/drivers/net/fm/p3060.c b/drivers/net/fm/p3060.c
deleted file mode 100644
index c9748a954c..0000000000
--- a/drivers/net/fm/p3060.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-u32 port_to_devdisr[] = {
-	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
-	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
-	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
-	[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
-	[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
-	[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
-	[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
-	[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
-};
-
-static int is_device_disabled(enum fm_port port)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 devdisr2 = in_be32(&gur->devdisr2);
-
-	return port_to_devdisr[port] & devdisr2;
-}
-
-void fman_disable_port(enum fm_port port)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-	/* don't allow disabling of DTSEC1 as its needed for MDIO */
-	if (port == FM1_DTSEC1)
-		return;
-
-	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
-}
-
-phy_interface_t fman_port_enet_if(enum fm_port port)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
-
-	if (is_device_disabled(port))
-		return PHY_INTERFACE_MODE_NONE;
-
-	/* handle RGMII/MII first */
-	if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
-		FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
-		return PHY_INTERFACE_MODE_RGMII;
-
-	if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
-		FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
-		return PHY_INTERFACE_MODE_RGMII;
-
-	if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
-		FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
-		return PHY_INTERFACE_MODE_RGMII;
-
-	switch (port) {
-	case FM1_DTSEC1:
-	case FM1_DTSEC2:
-	case FM1_DTSEC3:
-	case FM1_DTSEC4:
-		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
-			return PHY_INTERFACE_MODE_SGMII;
-		break;
-	case FM2_DTSEC1:
-	case FM2_DTSEC2:
-	case FM2_DTSEC3:
-	case FM2_DTSEC4:
-		if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
-			return PHY_INTERFACE_MODE_SGMII;
-		break;
-	default:
-		return PHY_INTERFACE_MODE_NONE;
-	}
-
-	return PHY_INTERFACE_MODE_NONE;
-}
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 1d75a82bc3..0d46c96312 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -211,6 +211,95 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
 	return 1;
 }
 
+#ifdef CONFIG_FSL_CORENET
+static void fsl_pcie_boot_master(pit_t *pi)
+{
+	/* configure inbound window for slave's u-boot image */
+	debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
+			"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
+			CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+	struct pci_region r_inbound;
+	u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
+					- 1;
+	pci_set_region(&r_inbound,
+		CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
+		CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+		sz_inbound,
+		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	set_inbound_window(pi--, &r_inbound,
+		CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+
+	/* configure inbound window for slave's u-boot image */
+	debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
+			"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
+			CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+	pci_set_region(&r_inbound,
+		CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
+		CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+		sz_inbound,
+		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	set_inbound_window(pi--, &r_inbound,
+		CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+
+	/* configure inbound window for slave's ucode and ENV */
+	debug("PCIEBOOT - MASTER: Inbound window for slave's "
+			"ucode and ENV; "
+			"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
+			(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
+			CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
+	sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
+				- 1;
+	pci_set_region(&r_inbound,
+		CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
+		CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
+		sz_inbound,
+		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	set_inbound_window(pi--, &r_inbound,
+		CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
+}
+
+static void fsl_pcie_boot_master_release_slave(int port)
+{
+	unsigned long release_addr;
+
+	/* now release slave's core 0 */
+	switch (port) {
+	case 1:
+		release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
+			+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
+		break;
+	case 2:
+		release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
+			+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
+		break;
+	case 3:
+		release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
+			+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
+		break;
+	default:
+		release_addr = 0;
+		break;
+	}
+	if (release_addr != 0) {
+		out_be32((void *)release_addr,
+			CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
+		debug("PCIEBOOT - MASTER: "
+			"Release slave successfully! Now the slave should start up!\n");
+	} else {
+		debug("PCIEBOOT - MASTER: "
+			"Release slave failed!\n");
+	}
+}
+#endif
+
 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 {
 	u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
@@ -295,8 +384,25 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	/* see if we are a PCIe or PCI controller */
 	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 
+#ifdef CONFIG_FSL_CORENET
+	/* boot from PCIE --master */
+	char *s = getenv("bootmaster");
+	char pcie[6];
+	sprintf(pcie, "PCIE%d", pci_info->pci_num);
+
+	if (s && (strcmp(s, pcie) == 0)) {
+		debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
+				pci_info->pci_num);
+		fsl_pcie_boot_master((pit_t *)pi);
+	} else {
+		/* inbound */
+		inbound = fsl_pci_setup_inbound_windows(hose,
+					out_lo, pcie_cap, pi);
+	}
+#else
 	/* inbound */
 	inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
+#endif
 
 	for (r = 0; r < hose->region_count; r++)
 		debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
@@ -488,6 +594,16 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	if (fsl_is_pci_agent(hose)) {
 		fsl_pci_config_unlock(hose);
 		hose->last_busno = hose->first_busno;
+#ifdef CONFIG_FSL_CORENET
+	} else {
+		/* boot from PCIE --master releases slave's core 0 */
+		char *s = getenv("bootmaster");
+		char pcie[6];
+		sprintf(pcie, "PCIE%d", pci_info->pci_num);
+
+		if (s && (strcmp(s, pcie) == 0))
+			fsl_pcie_boot_master_release_slave(pci_info->pci_num);
+#endif
 	}
 
 	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 216c8982be..e6ae709db7 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -580,8 +580,7 @@ static void phy_change(struct eth_device *dev)
 {
 	uec_private_t	*uec = (uec_private_t *)dev->priv;
 
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
@@ -592,8 +591,7 @@ static void phy_change(struct eth_device *dev)
 	/* Update the link, speed, duplex */
 	uec->mii_info->phyinfo->read_status(uec->mii_info);
 
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
 	/*
 	 * QE12 is muxed with LBCTL, it needs to be released for enabling
 	 * LBCTL signal for LBC usage.
@@ -1208,16 +1206,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 	uec_private_t		*uec;
 	int			err, i;
 	struct phy_info         *curphy;
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
 	uec = (uec_private_t *)dev->priv;
 
 	if (uec->the_first_run == 0) {
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
 	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
@@ -1249,8 +1245,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 			udelay(100000);
 		} while (1);
 
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
 		/* QE12 needs to be released for enabling LBCTL signal*/
 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 #endif