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authorMichal Simek <michal.simek@xilinx.com>2015-12-10 15:32:11 +0100
committerMichal Simek <michal.simek@xilinx.com>2016-01-27 15:55:52 +0100
commit5a4baa33e4d0beb9708719160bfc3f91a8f9f3bf (patch)
tree876fadcf9720a1a15c7990e599dc366f18bfeb65 /drivers
parent3af709092c6d92cf7e4e19a45fbb96e2e4d1c8f5 (diff)
net: emaclite: Use indirect register access for TX reset
Move to use indirect register access when timeout expires for resetting TX buffers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/xilinx_emaclite.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 724b61e0b7..72b6e0ac42 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -408,6 +408,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len)
u32 reg;
u32 baseaddress;
struct xemaclite *emaclite = dev->priv;
+ struct emaclite_regs *regs = emaclite->regs;
u32 maxtry = 1000;
@@ -422,10 +423,9 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len)
if (!maxtry) {
printf("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
- out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
+ out_be32(&regs->tx_ping_tsr, 0);
if (emaclite->txpp) {
- out_be32 (dev->iobase + XEL_TSR_OFFSET +
- XEL_BUFFER_OFFSET, 0);
+ out_be32(&regs->tx_pong_tsr, 0);
}
return -1;
}