diff options
| author | Wolfgang Denk <wd@denx.de> | 2008-03-26 15:38:47 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-03-26 15:38:47 +0100 |
| commit | 5b5eb9ca5b778f763bcf332697b35cc1e747626e (patch) | |
| tree | 7f76c220a73b7eca643c4c5b664ae9212d80e1f8 /drivers | |
| parent | da8808df7a9cef5a3d2ee286ef9ebf9de1780660 (diff) | |
Coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/rtc/ds1337.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 69ab2bf9db..e908749ef8 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001, 2002 + * (C) Copyright 2001-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Keith Outwater, keith_outwater@mvis.com` * @@ -60,19 +60,19 @@ /* * RTC control register bits */ -#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */ -#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */ -#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */ -#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */ -#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */ -#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */ +#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */ +#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */ +#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */ +#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */ +#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */ +#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */ /* * RTC status register bits */ -#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ -#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ -#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ +#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ +#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ +#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ static uchar rtc_read (uchar reg); @@ -163,7 +163,7 @@ void rtc_set (struct rtc_time *tmp) */ #ifdef CFG_RTC_DS1337_NOOSC #define RTC_DS1337_RESET_VAL \ - (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) + (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) #else #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) #endif |