diff options
| author | Suneel Garapati <sgarapati@marvell.com> | 2019-10-19 15:52:32 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-08-25 08:01:16 +0200 |
| commit | 636cc1773a461de83f69f69cd3f22f9bcad2f589 (patch) | |
| tree | 71ba78da8210729c9eaef5c2b0815075008e9125 /drivers | |
| parent | 4cf56ec07f673f99c87862dbb7e72bc077685474 (diff) | |
pci: pci-uclass: Add support for Enhanced Allocation in Bridges
If Enhanced Allocation capability is present in bridges, use it
to read the fixed sub-ordinate bus number.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/pci-uclass.c | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 19ea3ae9c1..fa6115a105 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -620,10 +620,19 @@ int dm_pci_hose_probe_bus(struct udevice *bus) { int sub_bus; int ret; + int ea_pos; + u8 reg; debug("%s\n", __func__); - sub_bus = pci_get_bus_max() + 1; + ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA); + if (ea_pos) { + dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8), + ®); + sub_bus = reg; + } else { + sub_bus = pci_get_bus_max() + 1; + } debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); dm_pciauto_prescan_setup_bridge(bus, sub_bus); @@ -633,12 +642,15 @@ int dm_pci_hose_probe_bus(struct udevice *bus) ret); return ret; } - if (sub_bus != bus->seq) { - printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", - __func__, bus->name, bus->seq, sub_bus); - return -EPIPE; + + if (!ea_pos) { + if (sub_bus != bus->seq) { + debug("%s: Internal error, bus '%s' got seq %d, expected %d\n", + __func__, bus->name, bus->seq, sub_bus); + return -EPIPE; + } + sub_bus = pci_get_bus_max(); } - sub_bus = pci_get_bus_max(); dm_pciauto_postscan_setup_bridge(bus, sub_bus); return sub_bus; |