diff options
| author | Heiko Stübner <heiko@sntech.de> | 2017-02-18 19:46:22 +0100 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-03-16 16:03:44 -0600 |
| commit | 6496498a626dbde4d0ed96406e4efee9ff2ab0c0 (patch) | |
| tree | 1ecdcb40409b9014fbf6e0d4c5e7be99b5e8fdeb /drivers | |
| parent | 27326c7ee269ff351bba8c2461e19f29d66b6a3a (diff) | |
rockchip: clk: rk3288: limit gpll and cpll init to SPL build
The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3288.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index d15504c3aa..78356766a7 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -131,8 +131,10 @@ enum { /* Keep divisors as low as possible to reduce jitter and power usage */ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); +#ifdef CONFIG_SPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +#endif static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) |