diff options
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-06-13 08:02:55 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-12-03 12:51:16 +0100 |
| commit | 6f8f20f85deeed9be351f8da36f2b38136207063 (patch) | |
| tree | 83c3110f5e5ced695efdb98d922b062923b8be25 /drivers | |
| parent | 8ec6a04b6bf641f13402506c0f1b1d9dda699b51 (diff) | |
mmc: tmio: Do not set divider to 1 in DDR mode
The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/tmio-common.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 3ba2f07460..424b60ce52 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -574,6 +574,10 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, divisor = DIV_ROUND_UP(mclk, mmc->clock); + /* Do not set divider to 0xff in DDR mode */ + if (mmc->ddr_mode && (divisor == 1)) + divisor = 2; + if (divisor <= 1) val = (priv->caps & TMIO_SD_CAP_RCAR) ? TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; |