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authorYe Li <ye.li@nxp.com>2019-01-07 03:18:06 +0000
committerPeng Fan <peng.fan@nxp.com>2019-05-03 20:03:41 +0800
commit72a89e0da5ac6a4ab929b15a2b656f04f50767f6 (patch)
tree311a4c938f6fb4afd4623f8f4179aa75757471f0 /drivers
parentb4ee6daad7a2604ca9466b2ba48de86cc27d381f (diff)
mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue
When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/fsl_esdhc.c23
1 files changed, 18 insertions, 5 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 9e34557d16..60972014c4 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -614,18 +614,31 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
#else
int pre_div = 2;
#endif
- int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
int sdhc_clk = priv->sdhc_clk;
uint clk;
+ /*
+ * For ddr mode, usdhc need to enable DDR mode first, after select
+ * this DDR mode, usdhc will automatically divide the usdhc clock
+ */
+ if (mmc->ddr_mode) {
+ writel(readl(&regs->mixctrl) | MIX_CTRL_DDREN, &regs->mixctrl);
+ sdhc_clk >>= 1;
+ }
+
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
- while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
- pre_div *= 2;
+ if (sdhc_clk / 16 > clock) {
+ for (; pre_div < 256; pre_div *= 2)
+ if ((sdhc_clk / pre_div) <= (clock * 16))
+ break;
+ } else
+ pre_div = 1;
- while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
- div++;
+ for (div = 1; div <= 16; div++)
+ if ((sdhc_clk / (div * pre_div)) <= clock)
+ break;
pre_div >>= 1;
div -= 1;