diff options
| author | Rick Chen <rick@andestech.com> | 2017-12-25 16:25:26 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-03-30 13:13:34 +0800 |
| commit | 7459c887c53e0615e9caa3a2a746db1e215c3d45 (patch) | |
| tree | 92cc4417aee3129b308a96a1dc286a5e2044f8fa /drivers | |
| parent | fcc7a077c4d91f12ceb9f18847d437e1c41ed53c (diff) | |
mmc: ftsdc010: Support High-Speed mode
ftsdc010 dm driver has been disable High-Speed mode
as default to work around Andes AE3XX platform's problem,
because of it does not support High-Speed mode in
commit id 73cd56b2df213c629191139e5c6705e069b6214f.
But other platforms or SoCs maybe support this function.
So High-Speed mode can be enabled from dts with
cap-mmc-highspeed or cap-sd-highspeed property.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/nds32_mmc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/nds32_mmc.c b/drivers/mmc/nds32_mmc.c index 6d3c8572e5..ec43e9d688 100644 --- a/drivers/mmc/nds32_mmc.c +++ b/drivers/mmc/nds32_mmc.c @@ -103,6 +103,11 @@ static int nds32_mmc_probe(struct udevice *dev) if (ret < 0) return ret; #endif + + if (dev_read_bool(dev, "cap-mmc-highspeed") || \ + dev_read_bool(dev, "cap-sd-highspeed")) + chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; + ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps, priv->minmax[1] , priv->minmax[0]); chip->mmc = &plat->mmc; |