diff options
| author | Wolfgang Denk <wd@denx.de> | 2012-06-07 23:34:11 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-06-07 23:34:11 +0200 |
| commit | 76aef69e49318863cb9966f872a80ddb5586d666 (patch) | |
| tree | f53fb2a645e9a0516e48aaefc862cdf6326fc528 /drivers | |
| parent | 25315683fd2197b2ecec0ac05427cbdebfb88274 (diff) | |
| parent | 99fc4fd168f2eff3237f05c6ec4e2bbffe9c06e5 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-sh
* 'master' of git://git.denx.de/u-boot-sh:
sh/ap_sh4a_4a: Fix typo of operator in ET0_ETXD4
sh: Add SH7269 device and RSK2+SH7269 board
sh: Set CONFIG_SH_ETHER_PHY_MODE and CONFIG_SH_ETHER_SH7734_MII to boards with sh_eth
sh: Add support for AP-SH4A-4A board
sh: Add register definition of PFC for SH7734
sh: r0p7734: Add support I2C controller
sh: Add bit control functions
sh: Add support for r0p7734 board
sh: Add support Renesas SH7734
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/serial/serial_sh.c | 4 | ||||
| -rw-r--r-- | drivers/serial/serial_sh.h | 20 |
2 files changed, 24 insertions, 0 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index fcf69abd25..13919c623b 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -35,6 +35,10 @@ # define SCIF_BASE SCIF4_BASE #elif defined(CONFIG_CONS_SCIF5) # define SCIF_BASE SCIF5_BASE +#elif defined(CONFIG_CONS_SCIF6) +# define SCIF_BASE SCIF6_BASE +#elif defined(CONFIG_CONS_SCIF7) +# define SCIF_BASE SCIF7_BASE #else # error "Default SCIF doesn't set....." #endif diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 0b3e779c8e..601da43be6 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -112,6 +112,15 @@ struct uart_port { # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) +#elif defined(CONFIG_CPU_SH7734) +# define SCSPTR0 0xFFE40020 +# define SCSPTR1 0xFFE41020 +# define SCSPTR2 0xFFE42020 +# define SCSPTR3 0xFFE43020 +# define SCSPTR4 0xFFE44020 +# define SCSPTR5 0xFFE45020 +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_CPU_SH4_202) # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* overrun error bit */ @@ -190,6 +199,16 @@ struct uart_port { # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ # endif # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7269) +# define SCSPTR0 0xe8007020 /* 16 bit SCIF */ +# define SCSPTR1 0xe8007820 /* 16 bit SCIF */ +# define SCSPTR2 0xe8008020 /* 16 bit SCIF */ +# define SCSPTR3 0xe8008820 /* 16 bit SCIF */ +# define SCSPTR4 0xe8009020 /* 16 bit SCIF */ +# define SCSPTR5 0xe8009820 /* 16 bit SCIF */ +# define SCSPTR6 0xe800a020 /* 16 bit SCIF */ +# define SCSPTR7 0xe800a820 /* 16 bit SCIF */ +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_CPU_SH7619) # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ @@ -216,6 +235,7 @@ struct uart_port { defined(CONFIG_CPU_SH7091) || \ defined(CONFIG_CPU_SH7750R) || \ defined(CONFIG_CPU_SH7722) || \ + defined(CONFIG_CPU_SH7734) || \ defined(CONFIG_CPU_SH7750S) || \ defined(CONFIG_CPU_SH7751) || \ defined(CONFIG_CPU_SH7751R) || \ |