diff options
| author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2008-01-15 23:25:25 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2008-01-15 23:30:40 +0900 |
| commit | 76e49aa7fb8e76cc49092c1acd53fff921e26360 (patch) | |
| tree | 58e64fc93d3c4e65656c8e295941fbde31e2f603 /drivers | |
| parent | 63a11be68306870e04d3851ed9fa41955cdf4894 (diff) | |
sh: Add support SH7710/SH7712
SH7710/SH7712 of SH3 CPU are supported.
SH771X is called SH-Ether, and has the Ether controller in CPU.
The driver of Ether is not included in this patch.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/serial/serial_sh.c | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index afba2d21b4..00a9b39195 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -30,25 +30,20 @@ #error "Default SCIF doesn't set....." #endif -#if defined(CONFIG_SH3) -/* There are SH7720's register */ -#define SCSMR (volatile unsigned short *)(SCIF_BASE + 0x0) -#define SCBRR (volatile unsigned char *)(SCIF_BASE + 0x4) -#define SCSCR (volatile unsigned short *)(SCIF_BASE + 0x8) -#define SCFSR (volatile unsigned short *)(SCIF_BASE + 0x14) /* SCSSR */ -#define SCFCR (volatile unsigned short *)(SCIF_BASE + 0x18) -#define SCFDR (volatile unsigned short *)(SCIF_BASE + 0x1C) -#define SCFTDR (volatile unsigned char *)(SCIF_BASE + 0x20) -#define SCFRDR (volatile unsigned char *)(SCIF_BASE + 0x24) +/* Base register */ +#define SCSMR (vu_short *)(SCIF_BASE + 0x0) +#define SCBRR (vu_char *)(SCIF_BASE + 0x4) +#define SCSCR (vu_short *)(SCIF_BASE + 0x8) +#define SCFCR (vu_short *)(SCIF_BASE + 0x18) +#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) +#ifdef CONFIG_SH7720 /* SH7720 specific */ +#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ +#define SCFTDR (vu_char *)(SCIF_BASE + 0x20) +#define SCFRDR (vu_char *)(SCIF_BASE + 0x24) #else -#define SCSMR (vu_short *)(SCIF_BASE + 0x0) -#define SCBRR (vu_char *)(SCIF_BASE + 0x4) -#define SCSCR (vu_short *)(SCIF_BASE + 0x8) #define SCFTDR (vu_char *)(SCIF_BASE + 0xC) #define SCFSR (vu_short *)(SCIF_BASE + 0x10) #define SCFRDR (vu_char *)(SCIF_BASE + 0x14) -#define SCFCR (vu_short *)(SCIF_BASE + 0x18) -#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) #endif #if defined(CONFIG_SH4A) @@ -62,7 +57,11 @@ #define SCLSR (vu_short *)(SCIF_BASE + 0x24) #define LSR_ORER 1 #elif defined (CONFIG_SH3) -#define SCLSR SCFSR /* SCSSR */ +#ifdef CONFIG_SH7720 /* SH7720 specific */ +# define SCLSR SCFSR /* SCSSR */ +#else +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +#endif #define LSR_ORER 0x0200 #endif |