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authorMarek Vasut <marex@denx.de>2019-03-09 21:58:09 +0100
committerMarek Vasut <marex@denx.de>2019-03-09 23:25:19 +0100
commit88c3bb49e1bf2b808cbad1fbdeda09480ae580a7 (patch)
tree65cb29a0d376e6842cc5e00d230d27d14b741300 /drivers
parent8297dd1d934281175ffa8646a2e3200755402db5 (diff)
ddr: socfpga: Clean up ddr_setup()
Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ddr/altera/sdram_arria10.c43
1 files changed, 15 insertions, 28 deletions
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index ff83c61002..1777e7e1a5 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -102,12 +102,6 @@ static int match_ddr_conf(u32 ddr_conf)
return 0;
}
-/* Check whether SDRAM is successfully Calibrated */
-static int is_sdram_cal_success(void)
-{
- return readl(&socfpga_ecc_hmc_base->ddrcalstat);
-}
-
static int emif_clear(void)
{
writel(0, DDR_REG_CORE2SEQ);
@@ -167,30 +161,23 @@ static int emif_reset(void)
static int ddr_setup(void)
{
- int i, j, ddr_setup_complete = 0;
-
- /* Try 3 times to do a calibration */
- for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
- WATCHDOG_RESET();
-
- /* A delay to wait for calibration bit to set */
- for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
- mdelay(500);
- ddr_setup_complete = is_sdram_cal_success();
- }
-
- if (!ddr_setup_complete)
- if (emif_reset())
- puts("Error: Failed to reset EMIF\n");
+ int i, ret;
+
+ /* Try 32 times to do a calibration */
+ for (i = 0; i < 32; i++) {
+ mdelay(500);
+ ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
+ BIT(0), true, 500, false);
+ if (!ret)
+ return 0;
+
+ ret = emif_reset();
+ if (ret)
+ puts("Error: Failed to reset EMIF\n");
}
- /* After 3 times trying calibration */
- if (!ddr_setup_complete) {
- puts("Error: Could Not Calibrate SDRAM\n");
- return -EPERM;
- }
-
- return 0;
+ puts("Error: Could Not Calibrate SDRAM\n");
+ return -EPERM;
}
static int sdram_is_ecc_enabled(void)