Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

17 files changed, 515 insertions, 15 deletions

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index d4ed9aec2a..59f2fd6610 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -194,7 +194,7 @@ step2:
 	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 	 * Let's wait for 800ms
 	 */
-	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 		(get_ddr_freq(0) >> 20)) << 1;
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 04e4178b15..d9cac2296a 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int x32_en = 0;	/* x32 enable */
 	unsigned int pchb8 = 0;		/* precharge bit 8 enable */
 	unsigned int hse;		/* Global half strength override */
+	unsigned int acc_ecc_en = 0;	/* Accumulated ECC enable */
 	unsigned int mem_halt = 0;	/* memory controller halt */
 	unsigned int bi = 0;		/* Bypass initialization */
 
@@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	ba_intlv_ctl = popts->ba_intlv_ctl;
 	hse = popts->half_strength_driver_enable;
 
+	/* set when ddr bus width < 64 */
+	acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
+
 	ddr->ddr_sdram_cfg = (0
 			| ((mem_en & 0x1) << 31)
 			| ((sren & 0x1) << 30)
@@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			| ((x32_en & 0x1) << 5)
 			| ((pchb8 & 0x1) << 4)
 			| ((hse & 0x1) << 3)
+			| ((acc_ecc_en & 0x1) << 2)
 			| ((mem_halt & 0x1) << 1)
 			| ((bi & 0x1) << 0)
 			);
@@ -2271,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	if (ip_rev > 0x40400)
 		unq_mrs_en = 1;
 
+	if (ip_rev > 0x40700)
+		ddr->debug[18] = popts->cswl_override;
+
 	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
 	set_ddr_sdram_mode(ddr, popts, common_dimm,
 				cas_latency, additive_latency, unq_mrs_en);
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 7fb418744e..6aa16b23dd 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS(wrlvl_override),
 		CTRL_OPTIONS(wrlvl_sample),
 		CTRL_OPTIONS(wrlvl_start),
+		CTRL_OPTIONS(cswl_override),
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(wrlvl_override),
 		CTRL_OPTIONS(wrlvl_sample),
 		CTRL_OPTIONS(wrlvl_start),
+		CTRL_OPTIONS_HEX(cswl_override),
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c14797ce0e..021b2fe511 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
 	(void *)IMX_I2C2_BASE
 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
 	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||	\
-	defined(CONFIG_MX6)
+	defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
 	(void *)I2C1_BASE_ADDR,
 	(void *)I2C2_BASE_ADDR,
 	(void *)I2C3_BASE_ADDR
@@ -545,7 +545,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
 	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
-	defined(CONFIG_MX6)
+	defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 			 mxc_i2c_read, mxc_i2c_write,
 			 mxc_i2c_set_bus_speed,
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 55416136ab..97d0389d9d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 	else if (cmd->resp_type & MMC_RSP_PRESENT)
 		xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 		xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 
 	voltage_caps = 0;
-	caps = regs->hostcapblt;
+	caps = esdhc_read32(&regs->hostcapblt);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 78bbd439f1..8d3dc0e308 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,6 @@
 #include <common.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_dtsec.h>
 #include <fsl_mdio.h>
 #include <phy.h>
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 316e06e17e..a9691c635a 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -8,8 +8,8 @@
 #define __FM_H__
 
 #include <common.h>
+#include <phy.h>
 #include <fm_eth.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_fman.h>
 
 /* Port ID */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index ff04695c32..6cf21c6f65 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
+#include <fsl_mdio.h>
 
 #include "fm.h"
 
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 592a67f2a5..9499290bba 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,6 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_memac.h>
 
 #include "fm.h"
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index f450f800e2..50171230ea 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,6 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_tgec.h>
 
 #include "fm.h"
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 1d88e6504b..d6b181b386 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,7 +11,6 @@
 #include <fsl_mdio.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/fsl_enet.h>
 
 void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 		int dev_addr, int regnum, int value)
@@ -20,7 +19,8 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 
 	out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
 	out_be32(&phyregs->miimcon, value);
-	asm("sync");
+	/* Memory barrier */
+	mb();
 
 	while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
 		;
@@ -38,11 +38,13 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 
 	/* Clear the command register, and wait */
 	out_be32(&phyregs->miimcom, 0);
-	asm("sync");
+	/* Memory barrier */
+	mb();
 
 	/* Initiate a read command, and wait */
 	out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
-	asm("sync");
+	/* Memory barrier */
+	mb();
 
 	/* Wait for the the indication that the read is done */
 	while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0338..79d656133a 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
 #include <fsl_mdio.h>
 #include <asm/errno.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 
 	do {
 		uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 }
 
 /* This returns the status bits of the device.	The return value
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 48a163411c..6b559f7974 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -13,7 +13,6 @@
 #include "qe.h"
 #include "uccf.h"
 #include <phy.h>
-#include <asm/fsl_enet.h>
 
 #define MAX_TX_THREADS				8
 #define MAX_RX_THREADS				8
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index da5f9a21f4..b0c6f6f4ab 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -17,10 +17,34 @@
 #define UC2_TE          (1 << 3)
 #define UC2_RE          (1 << 2)
 
+#define STAT_LBKDIF	(1 << 31)
+#define STAT_RXEDGIF	(1 << 30)
+#define STAT_TDRE	(1 << 23)
+#define STAT_RDRF	(1 << 21)
+#define STAT_IDLE	(1 << 20)
+#define STAT_OR		(1 << 19)
+#define STAT_NF		(1 << 18)
+#define STAT_FE		(1 << 17)
+#define STAT_PF		(1 << 16)
+#define STAT_MA1F	(1 << 15)
+#define STAT_MA2F	(1 << 14)
+#define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
+			STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
+
+#define CTRL_TE		(1 << 19)
+#define CTRL_RE		(1 << 18)
+
+#define FIFO_TXFE		0x80
+#define FIFO_RXFE		0x40
+
+#define WATER_TXWATER_OFF	1
+#define WATER_RXWATER_OFF	16
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
 
+#ifndef CONFIG_LPUART_32B_REG
 static void lpuart_serial_setbrg(void)
 {
 	u32 clk = mxc_get_clock(MXC_UART_CLK);
@@ -107,13 +131,107 @@ static struct serial_device lpuart_serial_drv = {
 	.getc = lpuart_serial_getc,
 	.tstc = lpuart_serial_tstc,
 };
+#else
+static void lpuart32_serial_setbrg(void)
+{
+	u32 clk = CONFIG_SYS_CLK_FREQ;
+	u32 sbr;
+
+	if (!gd->baudrate)
+		gd->baudrate = CONFIG_BAUDRATE;
+
+	sbr = (clk / (16 * gd->baudrate));
+	/* place adjustment later - n/32 BRFA */
+
+	out_be32(&base->baud, sbr);
+}
+
+static int lpuart32_serial_getc(void)
+{
+	u32 stat;
+
+	while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
+		out_be32(&base->stat, STAT_FLAGS);
+		WATCHDOG_RESET();
+	}
+
+	return in_be32(&base->data) & 0x3ff;
+}
+
+static void lpuart32_serial_putc(const char c)
+{
+	if (c == '\n')
+		serial_putc('\r');
+
+	while (!(in_be32(&base->stat) & STAT_TDRE))
+		WATCHDOG_RESET();
+
+	out_be32(&base->data, c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart32_serial_tstc(void)
+{
+	if ((in_be32(&base->water) >> 24) == 0)
+		return 0;
+
+	return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart32_serial_init(void)
+{
+	u8 ctrl;
+
+	ctrl = in_be32(&base->ctrl);
+	ctrl &= ~CTRL_RE;
+	ctrl &= ~CTRL_TE;
+	out_be32(&base->ctrl, ctrl);
+
+	out_be32(&base->modir, 0);
+	out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+	out_be32(&base->match, 0);
+	/* provide data bits, parity, stop bit, etc */
+
+	serial_setbrg();
+
+	out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
+
+	return 0;
+}
+
+static struct serial_device lpuart32_serial_drv = {
+	.name = "lpuart32_serial",
+	.start = lpuart32_serial_init,
+	.stop = NULL,
+	.setbrg = lpuart32_serial_setbrg,
+	.putc = lpuart32_serial_putc,
+	.puts = default_serial_puts,
+	.getc = lpuart32_serial_getc,
+	.tstc = lpuart32_serial_tstc,
+};
+#endif
 
 void lpuart_serial_initialize(void)
 {
+#ifdef CONFIG_LPUART_32B_REG
+	serial_register(&lpuart32_serial_drv);
+#else
 	serial_register(&lpuart_serial_drv);
+#endif
 }
 
 __weak struct serial_device *default_serial_console(void)
 {
+#ifdef CONFIG_LPUART_32B_REG
+	return &lpuart32_serial_drv;
+#else
 	return &lpuart_serial_drv;
+#endif
 }
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 93a91c3fa6..0914ea173d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
 				exynos_mipi_dsi_lowlevel.o
 obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
 obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
+obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
 obj-$(CONFIG_L5F31188) += l5f31188.o
 obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
new file mode 100644
index 0000000000..d4cd382776
--- /dev/null
+++ b/drivers/video/fsl_dcu_fb.c
@@ -0,0 +1,365 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <linux/fb.h>
+#include <malloc.h>
+#include <video_fb.h>
+#include "videomodes.h"
+
+/* Convert the X,Y resolution pair into a single number */
+#define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
+
+#ifdef CONFIG_SYS_FSL_DCU_LE
+#define	dcu_read32	in_le32
+#define	dcu_write32	out_le32
+#elif defined(CONFIG_SYS_FSL_DCU_BE)
+#define	dcu_read32	in_be32
+#define	dcu_write32	out_be32
+#endif
+
+#define DCU_MODE_BLEND_ITER(x)          ((x) << 20)
+#define DCU_MODE_RASTER_EN		(1 << 14)
+#define DCU_MODE_NORMAL			1
+#define DCU_MODE_COLORBAR               3
+#define DCU_BGND_R(x)			((x) << 16)
+#define DCU_BGND_G(x)			((x) << 8)
+#define DCU_BGND_B(x)			(x)
+#define DCU_DISP_SIZE_DELTA_Y(x)	((x) << 16)
+#define DCU_DISP_SIZE_DELTA_X(x)	(x)
+#define DCU_HSYN_PARA_BP(x)		((x) << 22)
+#define DCU_HSYN_PARA_PW(x)		((x) << 11)
+#define DCU_HSYN_PARA_FP(x)		(x)
+#define DCU_VSYN_PARA_BP(x)		((x) << 22)
+#define DCU_VSYN_PARA_PW(x)		((x) << 11)
+#define DCU_VSYN_PARA_FP(x)		(x)
+#define DCU_SYN_POL_INV_PXCK_FALL	(0 << 6)
+#define DCU_SYN_POL_NEG_REMAIN		(0 << 5)
+#define DCU_SYN_POL_INV_VS_LOW		(1 << 1)
+#define DCU_SYN_POL_INV_HS_LOW		(1)
+#define DCU_THRESHOLD_LS_BF_VS(x)	((x) << 16)
+#define DCU_THRESHOLD_OUT_BUF_HIGH(x)	((x) << 8)
+#define DCU_THRESHOLD_OUT_BUF_LOW(x)	(x)
+#define DCU_UPDATE_MODE_MODE            (1 << 31)
+#define DCU_UPDATE_MODE_READREG         (1 << 30)
+
+#define DCU_CTRLDESCLN_1_HEIGHT(x)	((x) << 16)
+#define DCU_CTRLDESCLN_1_WIDTH(x)	(x)
+#define DCU_CTRLDESCLN_2_POSY(x)	((x) << 16)
+#define DCU_CTRLDESCLN_2_POSX(x)	(x)
+#define DCU_CTRLDESCLN_4_EN		(1 << 31)
+#define DCU_CTRLDESCLN_4_TILE_EN	(1 << 30)
+#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT	(1 << 29)
+#define DCU_CTRLDESCLN_4_SAFETY_EN	(1 << 28)
+#define DCU_CTRLDESCLN_4_TRANS(x)	((x) << 20)
+#define DCU_CTRLDESCLN_4_BPP(x)		((x) << 16)
+#define DCU_CTRLDESCLN_4_RLE_EN		(1 << 15)
+#define DCU_CTRLDESCLN_4_LUOFFS(x)	((x) << 4)
+#define DCU_CTRLDESCLN_4_BB_ON		(1 << 2)
+#define DCU_CTRLDESCLN_4_AB(x)		(x)
+#define DCU_CTRLDESCLN_5_CKMAX_R(x)	((x) << 16)
+#define DCU_CTRLDESCLN_5_CKMAX_G(x)	((x) << 8)
+#define DCU_CTRLDESCLN_5_CKMAX_B(x)	(x)
+#define DCU_CTRLDESCLN_6_CKMIN_R(x)	((x) << 16)
+#define DCU_CTRLDESCLN_6_CKMIN_G(x)	((x) << 8)
+#define DCU_CTRLDESCLN_6_CKMIN_B(x)	(x)
+#define DCU_CTRLDESCLN_7_TILE_VER(x)	((x) << 16)
+#define DCU_CTRLDESCLN_7_TILE_HOR(x)	(x)
+#define DCU_CTRLDESCLN_8_FG_FCOLOR(x)	(x)
+#define DCU_CTRLDESCLN_9_BG_BCOLOR(x)	(x)
+
+#define BPP_16_RGB565			4
+#define BPP_24_RGB888			5
+#define BPP_32_ARGB8888			6
+
+/*
+ * This setting is used for the TWR_LCD_RGB card
+ */
+static struct fb_videomode fsl_dcu_mode_480_272 = {
+	.name		= "480x272-60",
+	.refresh	= 60,
+	.xres		= 480,
+	.yres		= 272,
+	.pixclock	= 91996,
+	.left_margin	= 2,
+	.right_margin	= 2,
+	.upper_margin	= 1,
+	.lower_margin	= 1,
+	.hsync_len	= 41,
+	.vsync_len	= 2,
+	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	.vmode		= FB_VMODE_NONINTERLACED
+};
+
+/*
+ * This setting is used for Siliconimage SiI9022A HDMI
+ */
+static struct fb_videomode fsl_dcu_mode_640_480 = {
+	.name		= "640x480-60",
+	.refresh	= 60,
+	.xres		= 640,
+	.yres		= 480,
+	.pixclock	= 39722,
+	.left_margin	= 48,
+	.right_margin	= 16,
+	.upper_margin	= 33,
+	.lower_margin	= 10,
+	.hsync_len	= 96,
+	.vsync_len	= 2,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED,
+};
+
+/*
+ * DCU register map
+ */
+struct dcu_reg {
+	u32 desc_cursor[4];
+	u32 mode;
+	u32 bgnd;
+	u32 disp_size;
+	u32 hsyn_para;
+	u32 vsyn_para;
+	u32 synpol;
+	u32 threshold;
+	u32 int_status;
+	u32 int_mask;
+	u32 colbar[8];
+	u32 div_ratio;
+	u32 sign_calc[2];
+	u32 crc_val;
+	u8 res_064[0x6c-0x64];
+	u32 parr_err_status1;
+	u8 res_070[0x7c-0x70];
+	u32 parr_err_status3;
+	u32 mparr_err_status1;
+	u8 res_084[0x90-0x84];
+	u32 mparr_err_status3;
+	u32 threshold_inp_buf[2];
+	u8 res_09c[0xa0-0x9c];
+	u32 luma_comp;
+	u32 chroma_red;
+	u32 chroma_green;
+	u32 chroma_blue;
+	u32 crc_pos;
+	u32 lyr_intpol_en;
+	u32 lyr_luma_comp;
+	u32 lyr_chrm_red;
+	u32 lyr_chrm_grn;
+	u32 lyr_chrm_blue;
+	u8 res_0c4[0xcc-0xc8];
+	u32 update_mode;
+	u32 underrun;
+	u8 res_0d4[0x100-0xd4];
+	u32 gpr;
+	u32 slr_l[2];
+	u32 slr_disp_size;
+	u32 slr_hvsync_para;
+	u32 slr_pol;
+	u32 slr_l_transp[2];
+	u8 res_120[0x200-0x120];
+	u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
+};
+
+static struct fb_info info;
+
+static void reset_total_layers(void)
+{
+	struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
+	int i;
+
+	for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
+		dcu_write32(&regs->ctrldescl[i][0], 0);
+		dcu_write32(&regs->ctrldescl[i][1], 0);
+		dcu_write32(&regs->ctrldescl[i][2], 0);
+		dcu_write32(&regs->ctrldescl[i][3], 0);
+		dcu_write32(&regs->ctrldescl[i][4], 0);
+		dcu_write32(&regs->ctrldescl[i][5], 0);
+		dcu_write32(&regs->ctrldescl[i][6], 0);
+		dcu_write32(&regs->ctrldescl[i][7], 0);
+		dcu_write32(&regs->ctrldescl[i][8], 0);
+		dcu_write32(&regs->ctrldescl[i][9], 0);
+		dcu_write32(&regs->ctrldescl[i][10], 0);
+	}
+
+	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
+}
+
+static int layer_ctrldesc_init(int index, u32 pixel_format)
+{
+	struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
+	unsigned int bpp = BPP_24_RGB888;
+
+	dcu_write32(&regs->ctrldescl[index][0],
+		    DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) |
+		    DCU_CTRLDESCLN_1_WIDTH(info.var.xres));
+
+	dcu_write32(&regs->ctrldescl[index][1],
+		    DCU_CTRLDESCLN_2_POSY(0) |
+		    DCU_CTRLDESCLN_2_POSX(0));
+
+	dcu_write32(&regs->ctrldescl[index][2], (unsigned int)info.screen_base);
+
+	switch (pixel_format) {
+	case 16:
+		bpp = BPP_16_RGB565;
+		break;
+	case 24:
+		bpp = BPP_24_RGB888;
+		break;
+	case 32:
+		bpp = BPP_32_ARGB8888;
+		break;
+	default:
+		printf("unsupported color depth: %u\n", pixel_format);
+	}
+
+	dcu_write32(&regs->ctrldescl[index][3],
+		    DCU_CTRLDESCLN_4_EN |
+		    DCU_CTRLDESCLN_4_TRANS(0xff) |
+		    DCU_CTRLDESCLN_4_BPP(bpp) |
+		    DCU_CTRLDESCLN_4_AB(0));
+
+	dcu_write32(&regs->ctrldescl[index][4],
+		    DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
+		    DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
+		    DCU_CTRLDESCLN_5_CKMAX_B(0xff));
+	dcu_write32(&regs->ctrldescl[index][5],
+		    DCU_CTRLDESCLN_6_CKMIN_R(0) |
+		    DCU_CTRLDESCLN_6_CKMIN_G(0) |
+		    DCU_CTRLDESCLN_6_CKMIN_B(0));
+
+	dcu_write32(&regs->ctrldescl[index][6],
+		    DCU_CTRLDESCLN_7_TILE_VER(0) |
+		    DCU_CTRLDESCLN_7_TILE_HOR(0));
+
+	dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
+	dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
+
+	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
+
+	return 0;
+}
+
+int fsl_dcu_init(unsigned int xres, unsigned int yres,
+		 unsigned int pixel_format)
+{
+	struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
+	unsigned int div, mode;
+
+	/* Memory allocation for framebuffer */
+	info.screen_size =
+		info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
+	info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
+			roundup(info.screen_size, ARCH_DMA_MINALIGN));
+	memset(info.screen_base, 0, info.screen_size);
+
+	reset_total_layers();
+	div = dcu_set_pixel_clock(info.var.pixclock);
+	dcu_write32(&regs->div_ratio, (div - 1));
+
+	dcu_write32(&regs->disp_size,
+		    DCU_DISP_SIZE_DELTA_Y(info.var.yres) |
+		    DCU_DISP_SIZE_DELTA_X(info.var.xres / 16));
+
+	dcu_write32(&regs->hsyn_para,
+		    DCU_HSYN_PARA_BP(info.var.left_margin) |
+		    DCU_HSYN_PARA_PW(info.var.hsync_len) |
+		    DCU_HSYN_PARA_FP(info.var.right_margin));
+
+	dcu_write32(&regs->vsyn_para,
+		    DCU_VSYN_PARA_BP(info.var.upper_margin) |
+		    DCU_VSYN_PARA_PW(info.var.vsync_len) |
+		    DCU_VSYN_PARA_FP(info.var.lower_margin));
+
+	dcu_write32(&regs->synpol,
+		    DCU_SYN_POL_INV_PXCK_FALL |
+		    DCU_SYN_POL_NEG_REMAIN |
+		    DCU_SYN_POL_INV_VS_LOW |
+		    DCU_SYN_POL_INV_HS_LOW);
+
+	dcu_write32(&regs->bgnd,
+		    DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
+
+	dcu_write32(&regs->mode,
+		    DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) |
+		    DCU_MODE_RASTER_EN);
+
+	dcu_write32(&regs->threshold,
+		    DCU_THRESHOLD_LS_BF_VS(0x3) |
+		    DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
+		    DCU_THRESHOLD_OUT_BUF_LOW(0));
+
+	mode = dcu_read32(&regs->mode);
+	dcu_write32(&regs->mode, mode | DCU_MODE_NORMAL);
+
+	layer_ctrldesc_init(0, pixel_format);
+
+	return 0;
+}
+
+void *video_hw_init(void)
+{
+	static GraphicDevice ctfb;
+	const char *options;
+	unsigned int depth = 0, freq = 0;
+	struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
+
+	if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
+				  &options))
+		return NULL;
+
+	/* Find the monitor port, which is a required option */
+	if (!options)
+		return NULL;
+	if (strncmp(options, "monitor=", 8) != 0)
+		return NULL;
+
+	switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) {
+	case RESOLUTION(480, 272):
+		fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
+		break;
+	case RESOLUTION(640, 480):
+		fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+		break;
+	default:
+		printf("unsupported resolution %ux%u\n",
+		       ctfb.winSizeX, ctfb.winSizeY);
+	}
+
+	info.var.xres = fsl_dcu_mode_db->xres;
+	info.var.yres = fsl_dcu_mode_db->yres;
+	info.var.bits_per_pixel = 32;
+	info.var.pixclock = fsl_dcu_mode_db->pixclock;
+	info.var.left_margin = fsl_dcu_mode_db->left_margin;
+	info.var.right_margin = fsl_dcu_mode_db->right_margin;
+	info.var.upper_margin = fsl_dcu_mode_db->upper_margin;
+	info.var.lower_margin = fsl_dcu_mode_db->lower_margin;
+	info.var.hsync_len = fsl_dcu_mode_db->hsync_len;
+	info.var.vsync_len = fsl_dcu_mode_db->vsync_len;
+	info.var.sync = fsl_dcu_mode_db->sync;
+	info.var.vmode = fsl_dcu_mode_db->vmode;
+	info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
+
+	if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY,
+			      options + 8, fsl_dcu_mode_db) < 0)
+		return NULL;
+
+	ctfb.frameAdrs = (unsigned int)info.screen_base;
+	ctfb.plnSizeX = ctfb.winSizeX;
+	ctfb.plnSizeY = ctfb.winSizeY;
+
+	ctfb.gdfBytesPP = 4;
+	ctfb.gdfIndex = GDF_32BIT_X888RGB;
+
+	ctfb.memSize = info.screen_size;
+
+	return &ctfb;
+}
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0276a10564..1dc0f5aa10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -7,7 +7,7 @@
 
 obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
 obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
-ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
 obj-y += imx_watchdog.o
 endif
 obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o