Merge tag 'u-boot-rockchip-20200722' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

- New rk3326 board: Hardkernel Odroid Go2;
- Update board config and dts for RockPI 4/N8/N10;
- Update led boot on support for roc-rk3399-pc;
- Enable SPI Flash suppor for rk3328 rock64 board;
- Update rockchip pcie phy to use generic framework;

12 files changed, 418 insertions, 388 deletions

diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 02d3b08efa..bf4f1069ea 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
 	return rk3328_saradc_get_clk(cru);
 }
 
+static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
+{
+	u32 div, val;
+
+	val = readl(&cru->clksel_con[24]);
+	div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
+
+	return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
+{
+	u32 src_clk_div;
+
+	src_clk_div = GPLL_HZ / hz;
+	assert(src_clk_div < 128);
+
+	rk_clrsetreg(&cru->clksel_con[24],
+		     CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
+		     CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
+		     (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
+
+	return rk3328_spi_get_clk(cru);
+}
+
 static ulong rk3328_clk_get_rate(struct clk *clk)
 {
 	struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
@@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
 	case SCLK_SARADC:
 		rate = rk3328_saradc_get_clk(priv->cru);
 		break;
+	case SCLK_SPI:
+		rate = rk3328_spi_get_clk(priv->cru);
+		break;
 	default:
 		return -ENOENT;
 	}
@@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_SARADC:
 		ret = rk3328_saradc_set_clk(priv->cru, rate);
 		break;
+	case SCLK_SPI:
+		ret = rk3328_spi_set_clk(priv->cru, rate);
+		break;
 	case DCLK_LCDC:
 	case SCLK_PDM:
 	case SCLK_RTC32K:
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 7e1e51d9ea..ff974e5d74 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -200,6 +200,7 @@ config PCIE_MEDIATEK
 config PCIE_ROCKCHIP
 	bool "Enable Rockchip PCIe driver"
 	select DM_PCI
+	select PHY_ROCKCHIP_PCIE
 	default y if ROCKCHIP_RK3399
 	help
 	  Say Y here if you want to enable PCIe controller support on
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 29092916a6..6378821aaf 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,5 +43,5 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
 obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
-obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
+obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
 obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 0edc2464a8..04609f1296 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -15,6 +15,7 @@
 #include <clk.h>
 #include <dm.h>
 #include <dm/device_compat.h>
+#include <generic-phy.h>
 #include <pci.h>
 #include <power-domain.h>
 #include <power/regulator.h>
@@ -25,10 +26,80 @@
 #include <asm/arch-rockchip/clock.h>
 #include <linux/iopoll.h>
 
-#include "pcie_rockchip.h"
-
 DECLARE_GLOBAL_DATA_PTR;
 
+#define HIWORD_UPDATE(mask, val)        (((mask) << 16) | (val))
+#define HIWORD_UPDATE_BIT(val)          HIWORD_UPDATE(val, val)
+
+#define ENCODE_LANES(x)                 ((((x) >> 1) & 3) << 4)
+#define PCIE_CLIENT_BASE                0x0
+#define PCIE_CLIENT_CONFIG              (PCIE_CLIENT_BASE + 0x00)
+#define PCIE_CLIENT_CONF_ENABLE         HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE   HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_MODE_RC             HIWORD_UPDATE_BIT(0x0040)
+#define PCIE_CLIENT_GEN_SEL_1           HIWORD_UPDATE(0x0080, 0)
+#define PCIE_CLIENT_BASIC_STATUS1	0x0048
+#define PCIE_CLIENT_LINK_STATUS_UP	GENMASK(21, 20)
+#define PCIE_CLIENT_LINK_STATUS_MASK	GENMASK(21, 20)
+#define PCIE_LINK_UP(x) \
+	(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_RC_NORMAL_BASE		0x800000
+#define PCIE_LM_BASE			0x900000
+#define PCIE_LM_VENDOR_ID              (PCIE_LM_BASE + 0x44)
+#define PCIE_LM_VENDOR_ROCKCHIP		0x1d87
+#define PCIE_LM_RCBAR			(PCIE_LM_BASE + 0x300)
+#define PCIE_LM_RCBARPIE		BIT(19)
+#define PCIE_LM_RCBARPIS		BIT(20)
+#define PCIE_RC_BASE			0xa00000
+#define PCIE_RC_CONFIG_DCR		(PCIE_RC_BASE + 0x0c4)
+#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT	18
+#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT	26
+#define PCIE_RC_PCIE_LCAP		(PCIE_RC_BASE + 0x0cc)
+#define PCIE_RC_PCIE_LCAP_APMS_L0S	BIT(10)
+#define PCIE_ATR_BASE			0xc00000
+#define PCIE_ATR_OB_ADDR0(i)		(PCIE_ATR_BASE + 0x000 + (i) * 0x20)
+#define PCIE_ATR_OB_ADDR1(i)		(PCIE_ATR_BASE + 0x004 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC0(i)		(PCIE_ATR_BASE + 0x008 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC1(i)		(PCIE_ATR_BASE + 0x00c + (i) * 0x20)
+#define PCIE_ATR_IB_ADDR0(i)		(PCIE_ATR_BASE + 0x800 + (i) * 0x8)
+#define PCIE_ATR_IB_ADDR1(i)		(PCIE_ATR_BASE + 0x804 + (i) * 0x8)
+#define PCIE_ATR_HDR_MEM		0x2
+#define PCIE_ATR_HDR_IO			0x6
+#define PCIE_ATR_HDR_CFG_TYPE0		0xa
+#define PCIE_ATR_HDR_CFG_TYPE1		0xb
+#define PCIE_ATR_HDR_RID		BIT(23)
+
+#define PCIE_ATR_OB_REGION0_SIZE	(32 * 1024 * 1024)
+#define PCIE_ATR_OB_REGION_SIZE		(1 * 1024 * 1024)
+
+struct rockchip_pcie {
+	fdt_addr_t axi_base;
+	fdt_addr_t apb_base;
+	int first_busno;
+	struct udevice *dev;
+
+	/* resets */
+	struct reset_ctl core_rst;
+	struct reset_ctl mgmt_rst;
+	struct reset_ctl mgmt_sticky_rst;
+	struct reset_ctl pipe_rst;
+	struct reset_ctl pm_rst;
+	struct reset_ctl pclk_rst;
+	struct reset_ctl aclk_rst;
+
+	/* gpio */
+	struct gpio_desc ep_gpio;
+
+	/* vpcie regulators */
+	struct udevice *vpcie12v;
+	struct udevice *vpcie3v3;
+	struct udevice *vpcie1v8;
+	struct udevice *vpcie0v9;
+
+	/* phy */
+	struct phy pcie_phy;
+};
+
 static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
 {
 	unsigned int bus = PCI_BUS(bdf);
@@ -159,8 +230,6 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
 static int rockchip_pcie_init_port(struct udevice *dev)
 {
 	struct rockchip_pcie *priv = dev_get_priv(dev);
-	struct rockchip_pcie_phy *phy = pcie_get_phy(priv);
-	struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy);
 	u32 cr, val, status;
 	int ret;
 
@@ -185,7 +254,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 		return ret;
 	}
 
-	ret = ops->init(phy);
+	ret = generic_phy_init(&priv->pcie_phy);
 	if (ret) {
 		dev_err(dev, "failed to init phy (ret=%d)\n", ret);
 		goto err_exit_phy;
@@ -242,7 +311,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 	cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
 	writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
 
-	ret = ops->power_on(phy);
+	ret = generic_phy_power_on(&priv->pcie_phy);
 	if (ret) {
 		dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
 		goto err_power_off_phy;
@@ -311,9 +380,9 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 	return 0;
 
 err_power_off_phy:
-	ops->power_off(phy);
+	generic_phy_power_off(&priv->pcie_phy);
 err_exit_phy:
-	ops->exit(phy);
+	generic_phy_exit(&priv->pcie_phy);
 	return ret;
 }
 
@@ -443,6 +512,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
 		return ret;
 	}
 
+	ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy);
+	if (ret) {
+		dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret);
+		return ret;
+	}
+
 	return 0;
 }
 
@@ -460,10 +535,6 @@ static int rockchip_pcie_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
-	ret = rockchip_pcie_phy_get(dev);
-	if (ret)
-		return ret;
-
 	ret = rockchip_pcie_set_vpcie(dev);
 	if (ret)
 		return ret;
diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h
deleted file mode 100644
index 845d5059e1..0000000000
--- a/drivers/pci/pcie_rockchip.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Rockchip PCIe Headers
- *
- * Copyright (c) 2016 Rockchip, Inc.
- * Copyright (c) 2020 Amarula Solutions(India)
- * Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
- * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
- *
- */
-
-#define HIWORD_UPDATE(mask, val)        (((mask) << 16) | (val))
-#define HIWORD_UPDATE_BIT(val)          HIWORD_UPDATE(val, val)
-
-#define ENCODE_LANES(x)                 ((((x) >> 1) & 3) << 4)
-#define PCIE_CLIENT_BASE                0x0
-#define PCIE_CLIENT_CONFIG              (PCIE_CLIENT_BASE + 0x00)
-#define PCIE_CLIENT_CONF_ENABLE         HIWORD_UPDATE_BIT(0x0001)
-#define PCIE_CLIENT_LINK_TRAIN_ENABLE   HIWORD_UPDATE_BIT(0x0002)
-#define PCIE_CLIENT_MODE_RC             HIWORD_UPDATE_BIT(0x0040)
-#define PCIE_CLIENT_GEN_SEL_1           HIWORD_UPDATE(0x0080, 0)
-#define PCIE_CLIENT_BASIC_STATUS1	0x0048
-#define PCIE_CLIENT_LINK_STATUS_UP	GENMASK(21, 20)
-#define PCIE_CLIENT_LINK_STATUS_MASK	GENMASK(21, 20)
-#define PCIE_LINK_UP(x) \
-	(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
-#define PCIE_RC_NORMAL_BASE		0x800000
-#define PCIE_LM_BASE			0x900000
-#define PCIE_LM_VENDOR_ID              (PCIE_LM_BASE + 0x44)
-#define PCIE_LM_VENDOR_ROCKCHIP		0x1d87
-#define PCIE_LM_RCBAR			(PCIE_LM_BASE + 0x300)
-#define PCIE_LM_RCBARPIE		BIT(19)
-#define PCIE_LM_RCBARPIS		BIT(20)
-#define PCIE_RC_BASE			0xa00000
-#define PCIE_RC_CONFIG_DCR		(PCIE_RC_BASE + 0x0c4)
-#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT	18
-#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT	26
-#define PCIE_RC_PCIE_LCAP		(PCIE_RC_BASE + 0x0cc)
-#define PCIE_RC_PCIE_LCAP_APMS_L0S	BIT(10)
-#define PCIE_ATR_BASE			0xc00000
-#define PCIE_ATR_OB_ADDR0(i)		(PCIE_ATR_BASE + 0x000 + (i) * 0x20)
-#define PCIE_ATR_OB_ADDR1(i)		(PCIE_ATR_BASE + 0x004 + (i) * 0x20)
-#define PCIE_ATR_OB_DESC0(i)		(PCIE_ATR_BASE + 0x008 + (i) * 0x20)
-#define PCIE_ATR_OB_DESC1(i)		(PCIE_ATR_BASE + 0x00c + (i) * 0x20)
-#define PCIE_ATR_IB_ADDR0(i)		(PCIE_ATR_BASE + 0x800 + (i) * 0x8)
-#define PCIE_ATR_IB_ADDR1(i)		(PCIE_ATR_BASE + 0x804 + (i) * 0x8)
-#define PCIE_ATR_HDR_MEM		0x2
-#define PCIE_ATR_HDR_IO			0x6
-#define PCIE_ATR_HDR_CFG_TYPE0		0xa
-#define PCIE_ATR_HDR_CFG_TYPE1		0xb
-#define PCIE_ATR_HDR_RID		BIT(23)
-
-#define PCIE_ATR_OB_REGION0_SIZE	(32 * 1024 * 1024)
-#define PCIE_ATR_OB_REGION_SIZE		(1 * 1024 * 1024)
-
-/*
- * The higher 16-bit of this register is used for write protection
- * only if BIT(x + 16) set to 1 the BIT(x) can be written.
- */
-#define HIWORD_UPDATE_MASK(val, mask, shift) \
-		((val) << (shift) | (mask) << ((shift) + 16))
-
-#define PHY_CFG_DATA_SHIFT    7
-#define PHY_CFG_ADDR_SHIFT    1
-#define PHY_CFG_DATA_MASK     0xf
-#define PHY_CFG_ADDR_MASK     0x3f
-#define PHY_CFG_RD_MASK       0x3ff
-#define PHY_CFG_WR_ENABLE     1
-#define PHY_CFG_WR_DISABLE    1
-#define PHY_CFG_WR_SHIFT      0
-#define PHY_CFG_WR_MASK       1
-#define PHY_CFG_PLL_LOCK      0x10
-#define PHY_CFG_CLK_TEST      0x10
-#define PHY_CFG_CLK_SCC       0x12
-#define PHY_CFG_SEPE_RATE     BIT(3)
-#define PHY_CFG_PLL_100M      BIT(3)
-#define PHY_PLL_LOCKED        BIT(9)
-#define PHY_PLL_OUTPUT        BIT(10)
-#define PHY_LANE_IDLE_OFF     0x1
-#define PHY_LANE_IDLE_MASK    0x1
-#define PHY_LANE_IDLE_A_SHIFT 3
-#define PHY_LANE_IDLE_B_SHIFT 4
-#define PHY_LANE_IDLE_C_SHIFT 5
-#define PHY_LANE_IDLE_D_SHIFT 6
-
-#define PCIE_PHY_CONF		0xe220
-#define PCIE_PHY_STATUS		0xe2a4
-#define PCIE_PHY_LANEOFF	0xe214
-
-struct rockchip_pcie_phy {
-	void *reg_base;
-	struct clk refclk;
-	struct reset_ctl phy_rst;
-	struct rockchip_pcie_phy_ops *ops;
-};
-
-struct rockchip_pcie_phy_ops {
-	int (*init)(struct rockchip_pcie_phy *phy);
-	int (*exit)(struct rockchip_pcie_phy *phy);
-	int (*power_on)(struct rockchip_pcie_phy *phy);
-	int (*power_off)(struct rockchip_pcie_phy *phy);
-};
-
-struct rockchip_pcie {
-	fdt_addr_t axi_base;
-	fdt_addr_t apb_base;
-	int first_busno;
-	struct udevice *dev;
-	struct rockchip_pcie_phy rk_phy;
-	struct rockchip_pcie_phy *phy;
-
-	/* resets */
-	struct reset_ctl core_rst;
-	struct reset_ctl mgmt_rst;
-	struct reset_ctl mgmt_sticky_rst;
-	struct reset_ctl pipe_rst;
-	struct reset_ctl pm_rst;
-	struct reset_ctl pclk_rst;
-	struct reset_ctl aclk_rst;
-
-	/* gpio */
-	struct gpio_desc ep_gpio;
-
-	/* vpcie regulators */
-	struct udevice *vpcie12v;
-	struct udevice *vpcie3v3;
-	struct udevice *vpcie1v8;
-	struct udevice *vpcie0v9;
-};
-
-int rockchip_pcie_phy_get(struct udevice *dev);
-
-static inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
-{
-	return pcie->phy;
-}
-
-static inline struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
-{
-	return (struct rockchip_pcie_phy_ops *)phy->ops;
-}
diff --git a/drivers/pci/pcie_rockchip_phy.c b/drivers/pci/pcie_rockchip_phy.c
deleted file mode 100644
index 47f5d6c7e3..0000000000
--- a/drivers/pci/pcie_rockchip_phy.c
+++ /dev/null
@@ -1,205 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Rockchip PCIe PHY driver
- *
- * Copyright (c) 2016 Rockchip, Inc.
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <dm/device_compat.h>
-#include <reset.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <linux/iopoll.h>
-#include <asm/arch-rockchip/clock.h>
-
-#include "pcie_rockchip.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data)
-{
-	u32 reg;
-
-	reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
-	reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
-	writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
-	udelay(1);
-
-	reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE,
-				 PHY_CFG_WR_MASK,
-				 PHY_CFG_WR_SHIFT);
-	writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
-	udelay(1);
-
-	reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE,
-				 PHY_CFG_WR_MASK,
-				 PHY_CFG_WR_SHIFT);
-	writel(reg, phy->reg_base + PCIE_PHY_CONF);
-}
-
-static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy)
-{
-	int ret = 0;
-	u32 reg, status;
-
-	ret = reset_deassert(&phy->phy_rst);
-	if (ret) {
-		dev_err(dev, "failed to assert phy reset\n");
-		return ret;
-	}
-
-	reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
-				 PHY_CFG_ADDR_MASK,
-				 PHY_CFG_ADDR_SHIFT);
-	writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
-	reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF,
-				 PHY_LANE_IDLE_MASK,
-				 PHY_LANE_IDLE_A_SHIFT);
-	writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
-
-	ret = -EINVAL;
-	ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
-				       status,
-				       status & PHY_PLL_LOCKED,
-				       20 * 1000,
-				       50);
-	if (ret) {
-		dev_err(&phy->dev, "pll lock timeout!\n");
-		goto err_pll_lock;
-	}
-
-	phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
-	phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
-
-	ret = -ETIMEDOUT;
-	ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
-				       status,
-				       !(status & PHY_PLL_OUTPUT),
-				       20 * 1000,
-				       50);
-	if (ret) {
-		dev_err(&phy->dev, "pll output enable timeout!\n");
-		goto err_pll_lock;
-	}
-
-	reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
-				 PHY_CFG_ADDR_MASK,
-				 PHY_CFG_ADDR_SHIFT);
-	writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
-	ret = -EINVAL;
-	ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
-				       status,
-				       status & PHY_PLL_LOCKED,
-				       20 * 1000,
-				       50);
-	if (ret) {
-		dev_err(&phy->dev, "pll relock timeout!\n");
-		goto err_pll_lock;
-	}
-
-	return 0;
-
-err_pll_lock:
-	reset_assert(&phy->phy_rst);
-	return ret;
-}
-
-static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy)
-{
-	int ret;
-	u32 reg;
-
-	reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF,
-				 PHY_LANE_IDLE_MASK,
-				 PHY_LANE_IDLE_A_SHIFT);
-	writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
-
-	ret = reset_assert(&phy->phy_rst);
-	if (ret) {
-		dev_err(dev, "failed to assert phy reset\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
-{
-	int ret;
-
-	ret = clk_enable(&phy->refclk);
-	if (ret) {
-		dev_err(dev, "failed to enable refclk clock\n");
-		return ret;
-	}
-
-	ret = reset_assert(&phy->phy_rst);
-	if (ret) {
-		dev_err(dev, "failed to assert phy reset\n");
-		goto err_reset;
-	}
-
-	return 0;
-
-err_reset:
-	clk_disable(&phy->refclk);
-	return ret;
-}
-
-static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
-{
-	clk_disable(&phy->refclk);
-
-	return 0;
-}
-
-static struct rockchip_pcie_phy_ops pcie_phy_ops = {
-	.init = rockchip_pcie_phy_init,
-	.power_on = rockchip_pcie_phy_power_on,
-	.power_off = rockchip_pcie_phy_power_off,
-	.exit = rockchip_pcie_phy_exit,
-};
-
-int rockchip_pcie_phy_get(struct udevice *dev)
-{
-	struct rockchip_pcie *priv = dev_get_priv(dev);
-	struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
-	ofnode phy_node;
-	u32 phandle;
-	int ret;
-
-	phandle = dev_read_u32_default(dev, "phys", 0);
-	phy_node = ofnode_get_by_phandle(phandle);
-	if (!ofnode_valid(phy_node)) {
-		dev_err(dev, "failed to found pcie-phy\n");
-		return -ENODEV;
-	}
-
-	phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-
-	ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
-	if (ret) {
-		dev_err(dev, "failed to get refclk clock phandle\n");
-		return ret;
-	}
-
-	ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
-	if (ret) {
-		dev_err(dev, "failed to get phy reset phandle\n");
-		return ret;
-	}
-
-	phy_priv->ops = &pcie_phy_ops;
-	priv->phy = phy_priv;
-
-	return 0;
-}
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 84cc7c876d..2318e71f35 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -11,6 +11,13 @@ config PHY_ROCKCHIP_INNO_USB2
 	help
 	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
 
+config PHY_ROCKCHIP_PCIE
+	bool "Rockchip PCIe PHY Driver"
+	depends on ARCH_ROCKCHIP
+	select PHY
+	help
+	  Enable this to support the Rockchip PCIe PHY.
+
 config PHY_ROCKCHIP_TYPEC
 	bool "Rockchip TYPEC PHY Driver"
 	depends on ARCH_ROCKCHIP
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 95b2f8a3c0..44049154f9 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -4,4 +4,5 @@
 #
 
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
new file mode 100644
index 0000000000..83928cffe0
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: (GPL-2.0-only)
+/*
+ * Rockchip PCIe PHY driver
+ *
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
+ * Copyright (C) 2016 ROCKCHIP, Inc.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(x + 16) set to 1 the BIT(x) can be written.
+ */
+#define HIWORD_UPDATE(val, mask, shift) \
+		((val) << (shift) | (mask) << ((shift) + 16))
+
+#define PHY_MAX_LANE_NUM      4
+#define PHY_CFG_DATA_SHIFT    7
+#define PHY_CFG_ADDR_SHIFT    1
+#define PHY_CFG_DATA_MASK     0xf
+#define PHY_CFG_ADDR_MASK     0x3f
+#define PHY_CFG_RD_MASK       0x3ff
+#define PHY_CFG_WR_ENABLE     1
+#define PHY_CFG_WR_DISABLE    1
+#define PHY_CFG_WR_SHIFT      0
+#define PHY_CFG_WR_MASK       1
+#define PHY_CFG_PLL_LOCK      0x10
+#define PHY_CFG_CLK_TEST      0x10
+#define PHY_CFG_CLK_SCC       0x12
+#define PHY_CFG_SEPE_RATE     BIT(3)
+#define PHY_CFG_PLL_100M      BIT(3)
+#define PHY_PLL_LOCKED        BIT(9)
+#define PHY_PLL_OUTPUT        BIT(10)
+#define PHY_LANE_RX_DET_SHIFT 11
+#define PHY_LANE_RX_DET_TH    0x1
+#define PHY_LANE_IDLE_OFF     0x1
+#define PHY_LANE_IDLE_MASK    0x1
+#define PHY_LANE_IDLE_A_SHIFT 3
+#define PHY_LANE_IDLE_B_SHIFT 4
+#define PHY_LANE_IDLE_C_SHIFT 5
+#define PHY_LANE_IDLE_D_SHIFT 6
+
+struct rockchip_pcie_phy_data {
+	unsigned int pcie_conf;
+	unsigned int pcie_status;
+	unsigned int pcie_laneoff;
+};
+
+struct rockchip_pcie_phy {
+	void *reg_base;
+	struct clk refclk;
+	struct reset_ctl phy_rst;
+	const struct rockchip_pcie_phy_data *data;
+};
+
+static void phy_wr_cfg(struct rockchip_pcie_phy *priv, u32 addr, u32 data)
+{
+	u32 reg;
+
+	reg = HIWORD_UPDATE(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
+	reg |= HIWORD_UPDATE(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
+	writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+	udelay(1);
+
+	reg = HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
+			    PHY_CFG_WR_MASK,
+			    PHY_CFG_WR_SHIFT);
+	writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+	udelay(1);
+
+	reg = HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
+			    PHY_CFG_WR_MASK,
+			    PHY_CFG_WR_SHIFT);
+	writel(reg, priv->reg_base + priv->data->pcie_conf);
+}
+
+static int rockchip_pcie_phy_power_on(struct phy *phy)
+{
+	struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+	int ret = 0;
+	u32 reg, status;
+
+	ret = reset_deassert(&priv->phy_rst);
+	if (ret) {
+		dev_err(dev, "failed to assert phy reset\n");
+		return ret;
+	}
+
+	reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
+			    PHY_CFG_ADDR_MASK,
+			    PHY_CFG_ADDR_SHIFT);
+	writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+	reg = HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
+			    PHY_LANE_IDLE_MASK,
+			    PHY_LANE_IDLE_A_SHIFT);
+	writel(reg, priv->reg_base + priv->data->pcie_laneoff);
+
+	ret = -EINVAL;
+	ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+				       status,
+				       status & PHY_PLL_LOCKED,
+				       20 * 1000,
+				       50);
+	if (ret) {
+		dev_err(&priv->dev, "pll lock timeout!\n");
+		goto err_pll_lock;
+	}
+
+	phy_wr_cfg(priv, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
+	phy_wr_cfg(priv, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
+
+	ret = -ETIMEDOUT;
+	ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+				       status,
+				       !(status & PHY_PLL_OUTPUT),
+				       20 * 1000,
+				       50);
+	if (ret) {
+		dev_err(&priv->dev, "pll output enable timeout!\n");
+		goto err_pll_lock;
+	}
+
+	reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
+			    PHY_CFG_ADDR_MASK,
+			    PHY_CFG_ADDR_SHIFT);
+	writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+	ret = -EINVAL;
+	ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+				       status,
+				       status & PHY_PLL_LOCKED,
+				       20 * 1000,
+				       50);
+	if (ret) {
+		dev_err(&priv->dev, "pll relock timeout!\n");
+		goto err_pll_lock;
+	}
+
+	return 0;
+
+err_pll_lock:
+	reset_assert(&priv->phy_rst);
+	return ret;
+}
+
+static int rockchip_pcie_phy_power_off(struct phy *phy)
+{
+	struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+	int ret;
+	u32 reg;
+
+	reg = HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
+			    PHY_LANE_IDLE_MASK,
+			    PHY_LANE_IDLE_A_SHIFT);
+	writel(reg, priv->reg_base + priv->data->pcie_laneoff);
+
+	ret = reset_assert(&priv->phy_rst);
+	if (ret) {
+		dev_err(dev, "failed to assert phy reset\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_pcie_phy_init(struct phy *phy)
+{
+	struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+	int ret;
+
+	ret = clk_enable(&priv->refclk);
+	if (ret) {
+		dev_err(dev, "failed to enable refclk clock\n");
+		return ret;
+	}
+
+	ret = reset_assert(&priv->phy_rst);
+	if (ret) {
+		dev_err(dev, "failed to assert phy reset\n");
+		goto err_reset;
+	}
+
+	return 0;
+
+err_reset:
+	clk_disable(&priv->refclk);
+	return ret;
+}
+
+static int rockchip_pcie_phy_exit(struct phy *phy)
+{
+	struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+
+	clk_disable(&priv->refclk);
+
+	return 0;
+}
+
+static struct phy_ops rockchip_pcie_phy_ops = {
+	.init = rockchip_pcie_phy_init,
+	.power_on = rockchip_pcie_phy_power_on,
+	.power_off = rockchip_pcie_phy_power_off,
+	.exit = rockchip_pcie_phy_exit,
+};
+
+static int rockchip_pcie_phy_probe(struct udevice *dev)
+{
+	struct rockchip_pcie_phy *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->data = (const struct rockchip_pcie_phy_data *)
+						dev_get_driver_data(dev);
+	if (!priv->data)
+		return -EINVAL;
+
+	priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	ret = clk_get_by_name(dev, "refclk", &priv->refclk);
+	if (ret) {
+		dev_err(dev, "failed to get refclk clock phandle\n");
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "phy", &priv->phy_rst);
+	if (ret) {
+		dev_err(dev, "failed to get phy reset phandle\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct rockchip_pcie_phy_data rk3399_pcie_data = {
+	.pcie_conf = 0xe220,
+	.pcie_status = 0xe2a4,
+	.pcie_laneoff = 0xe214,
+};
+
+static const struct udevice_id rockchip_pcie_phy_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-pcie-phy",
+		.data = (ulong)&rk3399_pcie_data,
+	},
+	{ /* sentile */ }
+};
+
+U_BOOT_DRIVER(rockchip_pcie_phy) = {
+	.name	= "rockchip_pcie_phy",
+	.id	= UCLASS_PHY,
+	.of_match = rockchip_pcie_phy_ids,
+	.ops = &rockchip_pcie_phy_ops,
+	.probe = rockchip_pcie_phy_probe,
+	.priv_auto_alloc_size = sizeof(struct rockchip_pcie_phy),
+};
diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c
index 6bc51572b2..b3e7421d08 100644
--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c
@@ -117,6 +117,19 @@ void sdram_print_stride(unsigned int stride)
 		printf("no stride\n");
 	}
 }
+#else
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+				 struct sdram_base_params *base)
+{
+}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
 #endif
 
 /*
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 0fe2cedc52..530c8a2f40 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2551,8 +2551,10 @@ static int lpddr4_set_rate(struct dram_info *dram,
 		lpddr4_set_ctl(dram, params, ctl_fn,
 			       dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
 
-		printf("%s: change freq to %d mhz %d, %d\n", __func__,
-		       dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, ctl_fn, phy_fn);
+		if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
+			printf("%s: change freq to %d mhz %d, %d\n", __func__,
+			       dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
+			       ctl_fn, phy_fn);
 	}
 
 	return 0;
@@ -2875,31 +2877,6 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *params)
 		if (stride == (-1))
 			goto error;
 	}
-	switch (stride) {
-	case 0xc:
-		printf("128B stride\n");
-		break;
-	case 5:
-	case 9:
-	case 0xd:
-	case 0x11:
-	case 0x19:
-		printf("256B stride\n");
-		break;
-	case 0xa:
-	case 0xe:
-	case 0x12:
-		printf("512B stride\n");
-		break;
-	case 0xf:
-		printf("4K stride\n");
-		break;
-	case 0x1f:
-		printf("32MB + 256B stride\n");
-		break;
-	default:
-		printf("no stride\n");
-	}
 
 	sdram_print_stride(stride);
 
@@ -2991,8 +2968,10 @@ static int sdram_init(struct dram_info *dram,
 			params->base.num_channels++;
 		}
 
-		printf("Channel ");
-		printf(channel ? "1: " : "0: ");
+		if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) {
+			printf("Channel ");
+			printf(channel ? "1: " : "0: ");
+		}
 
 		if (channel == 0)
 			set_ddr_stride(dram->pmusgrf, 0x17);
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index b6f95fa9a4..c5363c2419 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -545,7 +545,9 @@ const  struct rockchip_spi_params rk3399_spi_params = {
 };
 
 static const struct udevice_id rockchip_spi_ids[] = {
+	{ .compatible = "rockchip,rk3066-spi" },
 	{ .compatible = "rockchip,rk3288-spi" },
+	{ .compatible = "rockchip,rk3328-spi" },
 	{ .compatible = "rockchip,rk3368-spi",
 	  .data = (ulong)&rk3399_spi_params },
 	{ .compatible = "rockchip,rk3399-spi",