Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

- Fix SiFive HiFive Unleashed board booting failure problem.
- Enable SiFive fu540 PWM driver.
- Support SiFive fu540: SPI boot.
- Update OpenSBI used for RISC-V CI testing.
- Revert "riscv: Allow use of reset drivers".
- Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"".
- sysreset: syscon:
        - Don't assume default value for offset and mask property.
        - Support value property.
- qemu: Add syscon reboot and poweroff support.
- Fix SIFIVE debug serial dependency.
- Fix linking error when building u-boot-spl with no SMP support.
- AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg.
- Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi
- SiFive fu540 avoid using hardcoded ram base and size.

3 files changed, 41 insertions, 19 deletions

diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c
index f8f8ca9ad5..2eef1e7565 100644
--- a/drivers/ram/sifive/fu540_ddr.c
+++ b/drivers/ram/sifive/fu540_ddr.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <fdtdec.h>
 #include <init.h>
 #include <ram.h>
 #include <regmap.h>
@@ -39,9 +40,6 @@
 #define DENALI_PHY_1152	1152
 #define DENALI_PHY_1214	1214
 
-#define PAYLOAD_DEST	0x80000000
-#define DDR_MEM_SIZE	(8UL * 1024UL * 1024UL * 1024UL)
-
 #define DRAM_CLASS_OFFSET			8
 #define DRAM_CLASS_DDR4				0xA
 #define OPTIMAL_RMODW_EN_OFFSET			0
@@ -65,6 +63,8 @@
 #define PHY_RX_CAL_DQ0_0_OFFSET			0
 #define PHY_RX_CAL_DQ1_0_OFFSET			16
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct fu540_ddrctl {
 	volatile u32 denali_ctl[265];
 };
@@ -235,8 +235,8 @@ static int fu540_ddr_setup(struct udevice *dev)
 	struct fu540_ddr_params *params = &plat->ddr_params;
 	volatile u32 *denali_ctl =  priv->ctl->denali_ctl;
 	volatile u32 *denali_phy =  priv->phy->denali_phy;
-	const u64 ddr_size = DDR_MEM_SIZE;
-	const u64 ddr_end = PAYLOAD_DEST + ddr_size;
+	const u64 ddr_size = priv->info.size;
+	const u64 ddr_end = priv->info.base + ddr_size;
 	int ret, i;
 	u32 physet;
 
@@ -302,7 +302,7 @@ static int fu540_ddr_setup(struct udevice *dev)
 		     | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
 
 	/* set up range protection */
-	fu540_ddr_setup_range_protection(denali_ctl, DDR_MEM_SIZE);
+	fu540_ddr_setup_range_protection(denali_ctl, priv->info.size);
 
 	/* Mask off port command error interrupt DENALI_CTL_136 */
 	setbits_le32(DENALI_CTL_136 + denali_ctl,
@@ -314,14 +314,14 @@ static int fu540_ddr_setup(struct udevice *dev)
 
 	/* check size */
 	priv->info.size = get_ram_size((long *)priv->info.base,
-				       DDR_MEM_SIZE);
+				       ddr_size);
 
 	debug("%s : %lx\n", __func__, priv->info.size);
 
 	/* check memory access for all memory */
-	if (priv->info.size != DDR_MEM_SIZE) {
+	if (priv->info.size != ddr_size) {
 		printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
-		       priv->info.size, DDR_MEM_SIZE);
+		       priv->info.size, (uintptr_t)ddr_size);
 		return -EINVAL;
 	}
 
@@ -333,6 +333,11 @@ static int fu540_ddr_probe(struct udevice *dev)
 {
 	struct fu540_ddr_info *priv = dev_get_priv(dev);
 
+	/* Read memory base and size from DT */
+	fdtdec_setup_mem_size_base();
+	priv->info.base = gd->ram_base;
+	priv->info.size = gd->ram_size;
+
 #if defined(CONFIG_SPL_BUILD)
 	struct regmap *map;
 	int ret;
@@ -368,14 +373,9 @@ static int fu540_ddr_probe(struct udevice *dev)
 	priv->phy = regmap_get_range(map, 1);
 	priv->physical_filter_ctrl = regmap_get_range(map, 2);
 
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
-
-	priv->info.size = 0;
 	return fu540_ddr_setup(dev);
-#else
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
-	priv->info.size = DDR_MEM_SIZE;
 #endif
+
 	return 0;
 }
 
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 14df2e9247..e146ffc5f8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -359,7 +359,7 @@ config DEBUG_UART_SANDBOX
 
 config DEBUG_UART_SIFIVE
 	bool "SiFive UART"
-	depends on PL01X_SERIAL
+	depends on SIFIVE_SERIAL
 	help
 	  Select this to enable a debug UART using the serial_sifive driver. You
 	  will need to provide parameters to make this work. The driver will
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
index f64701aab3..1c47486614 100644
--- a/drivers/sysreset/sysreset_syscon.c
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -19,6 +19,7 @@ struct syscon_reboot_priv {
 	struct regmap *regmap;
 	unsigned int offset;
 	unsigned int mask;
+	unsigned int value;
 };
 
 static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
@@ -29,7 +30,7 @@ static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
 	if (type != driver_data)
 		return -EPROTONOSUPPORT;
 
-	regmap_write(priv->regmap, priv->offset, priv->mask);
+	regmap_update_bits(priv->regmap, priv->offset, priv->mask, priv->value);
 
 	return -EINPROGRESS;
 }
@@ -41,6 +42,8 @@ static struct sysreset_ops syscon_reboot_ops = {
 int syscon_reboot_probe(struct udevice *dev)
 {
 	struct syscon_reboot_priv *priv = dev_get_priv(dev);
+	int err;
+	int mask_err, value_err;
 
 	priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap");
 	if (IS_ERR(priv->regmap)) {
@@ -48,8 +51,27 @@ int syscon_reboot_probe(struct udevice *dev)
 		return -ENODEV;
 	}
 
-	priv->offset = dev_read_u32_default(dev, "offset", 0);
-	priv->mask = dev_read_u32_default(dev, "mask", 0);
+	err = dev_read_u32(dev, "offset", &priv->offset);
+	if (err) {
+		pr_err("unable to find offset\n");
+		return -ENOENT;
+	}
+
+	mask_err = dev_read_u32(dev, "mask", &priv->mask);
+	value_err = dev_read_u32(dev, "value", &priv->value);
+	if (mask_err && value_err) {
+		pr_err("unable to find mask and value\n");
+		return -EINVAL;
+	}
+
+	if (value_err) {
+		/* support old binding */
+		priv->value = priv->mask;
+		priv->mask = 0xffffffff;
+	} else if (mask_err) {
+		/* support value without mask*/
+		priv->mask = 0xffffffff;
+	}
 
 	return 0;
 }