diff options
| author | Marek Vasut <marex@denx.de> | 2015-07-20 08:03:11 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:15 +0200 |
| commit | b2dfd100bc43863f467f552a7bb26932810f2f5e (patch) | |
| tree | acb75eb92c82dc1da6ff361b8698b8d42e6d8a84 /drivers | |
| parent | 4b0ac26a15a74664e51b49f1698fc42776edd3bc (diff) | |
ddr: altera: Clean up set_rank_and_odt_mask() part 1
First, invert the logic of the if (odt_mode == ...) conditional to make
the OFF mode harder to miss. It is a short piece of code right at the
end, so move it up.
Also, clean up data types and constify where applicable and clean up
the cs_and_odt_mask assignment. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index b0105432bf..7dd9a66cc9 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -154,13 +154,16 @@ static void phy_mgr_initialize(void) param->dm_correct_mask = (1 << ratio) - 1; } -static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) +static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) { - uint32_t odt_mask_0 = 0; - uint32_t odt_mask_1 = 0; - uint32_t cs_and_odt_mask; + u32 odt_mask_0 = 0; + u32 odt_mask_1 = 0; + u32 cs_and_odt_mask; - if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) { + if (odt_mode == RW_MGR_ODT_MODE_OFF) { + odt_mask_0 = 0x0; + odt_mask_1 = 0x0; + } else { /* RW_MGR_ODT_MODE_READ_WRITE */ if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) { /* * 1 Rank @@ -242,15 +245,11 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) break; } } - } else { - odt_mask_0 = 0x0; - odt_mask_1 = 0x0; } - cs_and_odt_mask = - (0xFF & ~(1 << rank)) | - ((0xFF & odt_mask_0) << 8) | - ((0xFF & odt_mask_1) << 16); + cs_and_odt_mask = (0xFF & ~(1 << rank)) | + ((0xFF & odt_mask_0) << 8) | + ((0xFF & odt_mask_1) << 16); writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET); } |