diff options
| author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-01-30 13:07:06 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-02-09 07:50:57 -0500 |
| commit | bbd108a08225b1239b1ec1c10e8131fba6a3a95a (patch) | |
| tree | 3324114ed3c850227bebde0f28d258b303028b50 /drivers | |
| parent | e74b74c52876d776dda7a7ee5e2a8d555eaa5c4f (diff) | |
clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk_stm32mp1.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 09227cf8db..aebc6f0a34 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -165,6 +165,7 @@ /* used for ALL PLLNCR registers */ #define RCC_PLLNCR_PLLON BIT(0) #define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) #define RCC_PLLNCR_DIVPEN BIT(4) #define RCC_PLLNCR_DIVQEN BIT(5) #define RCC_PLLNCR_DIVREN BIT(6) @@ -1319,7 +1320,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) { const struct stm32mp1_clk_pll *pll = priv->data->pll; - writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); + clrsetbits_le32(priv->base + pll[pll_id].pllxcr, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | + RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); } static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) @@ -1438,6 +1442,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) RCC_PLLNCSGR_SSCG_MODE_MASK); writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); + + setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); } static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) |