Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>

7 files changed, 666 insertions, 147 deletions

diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 65896d1705..8887be901c 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -82,15 +82,19 @@
 #define CEVA_AXICC_CFG	0x3fffffff
 
 /* for ls1021a */
-#define LS1021_AHCI_VEND_AXICC 0xC0
+#define LS1021_AHCI_VEND_AXICC	0xC0
 #define LS1021_CEVA_PHY2_CFG	0x28183414
 #define LS1021_CEVA_PHY3_CFG	0x0e080e06
 #define LS1021_CEVA_PHY4_CFG	0x064a080b
 #define LS1021_CEVA_PHY5_CFG	0x2aa86470
 
+/* for ls1088a */
+#define LS1088_ECC_DIS_ADDR_CH2	0x100520
+#define LS1088_ECC_DIS_VAL_CH2	0x40000000
+
 /* ecc addr-val pair */
-#define ECC_DIS_ADDR_CH2	0x80000000
-#define ECC_DIS_VAL_CH2		0x20140520
+#define ECC_DIS_ADDR_CH2	0x20140520
+#define ECC_DIS_VAL_CH2		0x80000000
 #define SATA_ECC_REG_ADDR	0x20220520
 #define SATA_ECC_DISABLE	0x00020000
 
@@ -99,6 +103,9 @@ enum ceva_soc {
 	CEVA_LS1012A,
 	CEVA_LS1021A,
 	CEVA_LS1043A,
+	CEVA_LS1046A,
+	CEVA_LS1088A,
+	CEVA_LS2080A,
 };
 
 struct ceva_sata_priv {
@@ -138,7 +145,18 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
 
 	case CEVA_LS1012A:
 	case CEVA_LS1043A:
-		writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
+	case CEVA_LS1046A:
+		writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2);
+		/* fallthrough */
+	case CEVA_LS2080A:
+		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+		if (priv->flag & FLAG_COHERENT)
+			writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
+		break;
+
+	case CEVA_LS1088A:
+		writel(LS1088_ECC_DIS_VAL_CH2, LS1088_ECC_DIS_ADDR_CH2);
 		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
 		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
 		if (priv->flag & FLAG_COHERENT)
@@ -170,6 +188,9 @@ static const struct udevice_id sata_ceva_ids[] = {
 	{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
 	{ .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
 	{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
+	{ .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
+	{ .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
+	{ .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
 	{ }
 };
 
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index a3d2bd5fe6..c5bd8a8876 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -34,6 +34,7 @@ config SYS_NUM_DDR_CTLRS
 			ARCH_P4080	|| \
 			ARCH_P5020	|| \
 			ARCH_P5040	|| \
+			ARCH_LX2160A	|| \
 			ARCH_T4160
 	default 1
 
diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
index 7d66c3cf76..0c3394f2a8 100644
--- a/drivers/misc/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c
@@ -7,185 +7,401 @@
 #include <common.h>
 #include <fsl_ifc.h>
 
-void print_ifc_regs(void)
-{
-	int i, j;
-
-	printf("IFC Controller Registers\n");
-	for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
-		printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
-			i, get_ifc_cspr(i), i, get_ifc_amask(i),
-			i, get_ifc_csor(i));
-		for (j = 0; j < 4; j++)
-			printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
-	}
-}
-
-void init_early_memctl_regs(void)
-{
+struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"cs0",
 #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
-	set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
-
-#ifndef CONFIG_A003399_NOR_WORKAROUND
+		CONFIG_SYS_CSPR0,
 #ifdef CONFIG_SYS_CSPR0_EXT
-	set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
-#endif
+		CONFIG_SYS_CSPR0_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK0
+		CONFIG_SYS_AMASK0,
+#else
+		0,
+#endif
+		CONFIG_SYS_CSOR0,
+		{
+			CONFIG_SYS_CS0_FTIM0,
+			CONFIG_SYS_CS0_FTIM1,
+			CONFIG_SYS_CS0_FTIM2,
+			CONFIG_SYS_CS0_FTIM3,
+		},
 #ifdef CONFIG_SYS_CSOR0_EXT
-	set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+		CONFIG_SYS_CSOR0_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_CSPR0_FINAL
+		CONFIG_SYS_CSPR0_FINAL,
+#else
+		0,
 #endif
-	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
-	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
-	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#ifdef CONFIG_SYS_AMASK0_FINAL
+		CONFIG_SYS_AMASK0_FINAL,
+#else
+		0,
 #endif
 #endif
+	},
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2
+	{
+		"cs1",
+#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
+		CONFIG_SYS_CSPR1,
 #ifdef CONFIG_SYS_CSPR1_EXT
-	set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
-#endif
+		CONFIG_SYS_CSPR1_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK1
+		CONFIG_SYS_AMASK1,
+#else
+		0,
+#endif
+		CONFIG_SYS_CSOR1,
+		{
+			CONFIG_SYS_CS1_FTIM0,
+			CONFIG_SYS_CS1_FTIM1,
+			CONFIG_SYS_CS1_FTIM2,
+			CONFIG_SYS_CS1_FTIM3,
+		},
 #ifdef CONFIG_SYS_CSOR1_EXT
-	set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+		CONFIG_SYS_CSOR1_EXT,
+#else
+		0,
 #endif
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
-	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
-
-	set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
-	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
-	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+#ifdef CONFIG_SYS_CSPR1_FINAL
+		CONFIG_SYS_CSPR1_FINAL,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK1_FINAL
+		CONFIG_SYS_AMASK1_FINAL,
+#else
+		0,
+#endif
+#endif
+	},
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3
+	{
+		"cs2",
+#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
+		CONFIG_SYS_CSPR2,
 #ifdef CONFIG_SYS_CSPR2_EXT
-	set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
-#endif
+		CONFIG_SYS_CSPR2_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK2
+		CONFIG_SYS_AMASK2,
+#else
+		0,
+#endif
+		CONFIG_SYS_CSOR2,
+		{
+			CONFIG_SYS_CS2_FTIM0,
+			CONFIG_SYS_CS2_FTIM1,
+			CONFIG_SYS_CS2_FTIM2,
+			CONFIG_SYS_CS2_FTIM3,
+		},
 #ifdef CONFIG_SYS_CSOR2_EXT
-	set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+		CONFIG_SYS_CSOR2_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_CSPR2_FINAL
+		CONFIG_SYS_CSPR2_FINAL,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK2_FINAL
+		CONFIG_SYS_AMASK2_FINAL,
+#else
+		0,
 #endif
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
-	set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
-
-	set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
-	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
-	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+#endif
+	},
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4
+	{
+		"cs3",
+#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
+		CONFIG_SYS_CSPR3,
 #ifdef CONFIG_SYS_CSPR3_EXT
-	set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
-#endif
+		CONFIG_SYS_CSPR3_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK3
+		CONFIG_SYS_AMASK3,
+#else
+		0,
+#endif
+		CONFIG_SYS_CSOR3,
+		{
+			CONFIG_SYS_CS3_FTIM0,
+			CONFIG_SYS_CS3_FTIM1,
+			CONFIG_SYS_CS3_FTIM2,
+			CONFIG_SYS_CS3_FTIM3,
+		},
 #ifdef CONFIG_SYS_CSOR3_EXT
-	set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+		CONFIG_SYS_CSOR3_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_CSPR3_FINAL
+		CONFIG_SYS_CSPR3_FINAL,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK3_FINAL
+		CONFIG_SYS_AMASK3_FINAL,
+#else
+		0,
 #endif
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
-	set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
-
-	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
-	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
-	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+#endif
+	},
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5
+	{
+		"cs4",
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+		CONFIG_SYS_CSPR4,
 #ifdef CONFIG_SYS_CSPR4_EXT
-	set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
-#endif
+		CONFIG_SYS_CSPR4_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK4
+		CONFIG_SYS_AMASK4,
+#else
+		0,
+#endif
+		CONFIG_SYS_CSOR4,
+		{
+			CONFIG_SYS_CS4_FTIM0,
+			CONFIG_SYS_CS4_FTIM1,
+			CONFIG_SYS_CS4_FTIM2,
+			CONFIG_SYS_CS4_FTIM3,
+		},
 #ifdef CONFIG_SYS_CSOR4_EXT
-	set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+		CONFIG_SYS_CSOR4_EXT,
+#else
+		0,
 #endif
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
-	set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
-
-	set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
-	set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
-	set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#ifdef CONFIG_SYS_CSPR4_FINAL
+		CONFIG_SYS_CSPR4_FINAL,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK4_FINAL
+		CONFIG_SYS_AMASK4_FINAL,
+#else
+		0,
+#endif
+#endif
+	},
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 6
+	{
+		"cs5",
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+		CONFIG_SYS_CSPR5,
 #ifdef CONFIG_SYS_CSPR5_EXT
-	set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
-#endif
+		CONFIG_SYS_CSPR5_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK5
+		CONFIG_SYS_AMASK5,
+#else
+		0,
+#endif
+		CONFIG_SYS_CSOR5,
+		{
+			CONFIG_SYS_CS5_FTIM0,
+			CONFIG_SYS_CS5_FTIM1,
+			CONFIG_SYS_CS5_FTIM2,
+			CONFIG_SYS_CS5_FTIM3,
+		},
 #ifdef CONFIG_SYS_CSOR5_EXT
-	set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
+		CONFIG_SYS_CSOR5_EXT,
+#else
+		0,
 #endif
-#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
-	set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
-	set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
-	set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
-	set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
-
-	set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
-	set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
-	set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#ifdef CONFIG_SYS_CSPR5_FINAL
+		CONFIG_SYS_CSPR5_FINAL,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK5_FINAL
+		CONFIG_SYS_AMASK5_FINAL,
+#else
+		0,
+#endif
+#endif
+	},
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7
+	{
+		"cs6",
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+		CONFIG_SYS_CSPR6,
 #ifdef CONFIG_SYS_CSPR6_EXT
-	set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
-#endif
+		CONFIG_SYS_CSPR6_EXT,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK6
+		CONFIG_SYS_AMASK6,
+#else
+		0,
+#endif
+		CONFIG_SYS_CSOR6,
+		{
+			CONFIG_SYS_CS6_FTIM0,
+			CONFIG_SYS_CS6_FTIM1,
+			CONFIG_SYS_CS6_FTIM2,
+			CONFIG_SYS_CS6_FTIM3,
+		},
 #ifdef CONFIG_SYS_CSOR6_EXT
-	set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+		CONFIG_SYS_CSOR6_EXT,
+#else
+		0,
 #endif
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
-	set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
-
-	set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
-	set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
-	set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#ifdef CONFIG_SYS_CSPR6_FINAL
+		CONFIG_SYS_CSPR6_FINAL,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK6_FINAL
+		CONFIG_SYS_AMASK6_FINAL,
+#else
+		0,
+#endif
+#endif
+	},
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8
+	{
+		"cs7",
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+		CONFIG_SYS_CSPR7,
 #ifdef CONFIG_SYS_CSPR7_EXT
-	set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+		CONFIG_SYS_CSPR7_EXT,
+#else
+		0,
 #endif
-#ifdef CONFIG_SYS_CSOR7_EXT
-	set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#ifdef CONFIG_SYS_AMASK7
+		CONFIG_SYS_AMASK7,
+#else
+		0,
 #endif
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
-	set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+		CONFIG_SYS_CSOR7,
+#ifdef CONFIG_SYS_CSOR7_EXT
+		CONFIG_SYS_CSOR7_EXT,
+#else
+		0,
+#endif
+		{
+			CONFIG_SYS_CS7_FTIM0,
+			CONFIG_SYS_CS7_FTIM1,
+			CONFIG_SYS_CS7_FTIM2,
+			CONFIG_SYS_CS7_FTIM3,
+		},
+#ifdef CONFIG_SYS_CSPR7_FINAL
+		CONFIG_SYS_CSPR7_FINAL,
+#else
+		0,
+#endif
+#ifdef CONFIG_SYS_AMASK7_FINAL
+		CONFIG_SYS_AMASK7_FINAL,
+#else
+		0,
+#endif
+#endif
+	},
+#endif
+};
 
-	set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
-	set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
-	set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
-#endif
+__weak void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+	regs_info->regs = ifc_cfg_default_boot;
+	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+
+void print_ifc_regs(void)
+{
+	int i, j;
+
+	printf("IFC Controller Registers\n");
+	for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
+		printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
+		       i, get_ifc_cspr(i), i, get_ifc_amask(i),
+		       i, get_ifc_csor(i));
+		for (j = 0; j < 4; j++)
+			printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
+	}
+}
+
+void init_early_memctl_regs(void)
+{
+	int i, j;
+	struct ifc_regs *regs;
+	struct ifc_regs_info regs_info = {0};
+
+	ifc_cfg_boot_info(&regs_info);
+	regs = regs_info.regs;
+
+	for (i = 0 ; i < regs_info.cs_size; i++) {
+		if (regs[i].pr && (regs[i].pr & CSPR_V)) {
+			/* skip setting cspr/csor_ext in below condition */
+			if (!(CONFIG_IS_ENABLED(A003399_NOR_WORKAROUND) &&
+			      i == 0 &&
+			      ((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) {
+				if (regs[i].pr_ext)
+					set_ifc_cspr_ext(i, regs[i].pr_ext);
+				if (regs[i].or_ext)
+					set_ifc_csor_ext(i, regs[i].or_ext);
+			}
+
+			for (j = 0; j < ARRAY_SIZE(regs->ftim); j++)
+				set_ifc_ftim(i, j, regs[i].ftim[j]);
+
+			set_ifc_csor(i, regs[i].or);
+			set_ifc_amask(i, regs[i].amask);
+			set_ifc_cspr(i, regs[i].pr);
+		}
+	}
 }
 
 void init_final_memctl_regs(void)
 {
-#ifdef CONFIG_SYS_CSPR0_FINAL
-	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
-#endif
-#ifdef CONFIG_SYS_AMASK0_FINAL
-	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
-#endif
-#ifdef CONFIG_SYS_CSPR1_FINAL
-	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
-#endif
-#ifdef CONFIG_SYS_AMASK1_FINAL
-	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
-#endif
-#ifdef CONFIG_SYS_CSPR2_FINAL
-	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
-#endif
-#ifdef CONFIG_SYS_AMASK2_FINAL
-	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
-#endif
-#ifdef CONFIG_SYS_CSPR3_FINAL
-	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
-#endif
-#ifdef CONFIG_SYS_AMASK3_FINAL
-	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
-#endif
+	int i;
+	struct ifc_regs *regs;
+	struct ifc_regs_info regs_info;
+
+	ifc_cfg_boot_info(&regs_info);
+	regs = regs_info.regs;
+
+	for (i = 0 ; i < regs_info.cs_size && i < ARRAY_SIZE(regs->ftim); i++) {
+		if (!(regs[i].pr_final & CSPR_V))
+			continue;
+		if (regs[i].pr_final)
+			set_ifc_cspr(i, regs[i].pr_final);
+		if (regs[i].amask_final)
+			set_ifc_amask(i, (i == 1) ? regs[i].amask_final :
+								regs[i].amask);
+	}
 }
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index c5cf188f05..e19d7777dc 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -11,12 +11,14 @@
 #include "fm.h"
 #include <fsl_qe.h>		/* For struct qe_firmware */
 
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
-#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
 #include <spi_flash.h>
-#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
 #include <mmc.h>
+#include <environment.h>
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
 #endif
 
 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
@@ -347,6 +349,100 @@ static void fm_init_qmi(struct fm_qmi_common *qmi)
 }
 
 /* Init common part of FM, index is fm num# like fm as above */
+#ifdef CONFIG_TFABOOT
+int fm_init_common(int index, struct ccsr_fman *reg)
+{
+	int rc;
+	void *addr = NULL;
+	enum boot_src src = get_boot_src();
+
+	if (src == BOOT_SOURCE_IFC_NOR) {
+		addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
+				CONFIG_SYS_FSL_IFC_BASE);
+	} else if (src == BOOT_SOURCE_IFC_NAND) {
+		size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
+
+		addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+
+		rc = nand_read(get_nand_dev_by_index(0),
+			       (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+			       &fw_length, (u_char *)addr);
+		if (rc == -EUCLEAN) {
+			printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
+			       CONFIG_SYS_FMAN_FW_ADDR, rc);
+		}
+	} else if (src == BOOT_SOURCE_QSPI_NOR) {
+		struct spi_flash *ucode_flash;
+
+		addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+		int ret = 0;
+
+#ifdef CONFIG_DM_SPI_FLASH
+		struct udevice *new;
+
+		/* speed and mode will be read from DT */
+		ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
+					     CONFIG_ENV_SPI_CS, 0, 0, &new);
+
+		ucode_flash = dev_get_uclass_priv(new);
+#else
+		ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+					      CONFIG_ENV_SPI_CS,
+					      CONFIG_ENV_SPI_MAX_HZ,
+					      CONFIG_ENV_SPI_MODE);
+#endif
+		if (!ucode_flash) {
+			printf("SF: probe for ucode failed\n");
+		} else {
+			ret = spi_flash_read(ucode_flash,
+					     CONFIG_SYS_FMAN_FW_ADDR +
+					     CONFIG_SYS_FSL_QSPI_BASE,
+					     CONFIG_SYS_QE_FMAN_FW_LENGTH,
+					     addr);
+			if (ret)
+				printf("SF: read for ucode failed\n");
+			spi_flash_free(ucode_flash);
+		}
+	} else if (src == BOOT_SOURCE_SD_MMC) {
+		int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+		addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+		u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+		u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
+		struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+		if (!mmc) {
+			printf("\nMMC cannot find device for ucode\n");
+		} else {
+			printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
+			       dev, blk, cnt);
+			mmc_init(mmc);
+			(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
+						addr);
+		}
+	} else {
+		addr = NULL;
+	}
+
+	/* Upload the Fman microcode if it's present */
+	rc = fman_upload_firmware(index, &reg->fm_imem, addr);
+	if (rc)
+		return rc;
+	env_set_addr("fman_ucode", addr);
+
+	fm_init_muram(index, &reg->muram);
+	fm_init_qmi(&reg->fm_qmi_common);
+	fm_init_fpm(&reg->fm_fpm);
+
+	/* clear DMA status */
+	setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
+
+	/* set DMA mode */
+	setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
+
+	return fm_init_bmi(index, &reg->fm_bmi_common);
+}
+#else
 int fm_init_common(int index, struct ccsr_fman *reg)
 {
 	int rc;
@@ -429,3 +525,4 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 
 	return fm_init_bmi(index, &reg->fm_bmi_common);
 }
+#endif
diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 477ee4faed..1d85b2cfa8 100644
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -1,8 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+
-#
+# Copyright 2015-2018 NXP
 # Copyright 2014 Freescale Semiconductor, Inc.
 
 obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
 obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
 obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
+obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o
diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c
new file mode 100644
index 0000000000..7dd46c04f6
--- /dev/null
+++ b/drivers/net/ldpaa_eth/lx2160a.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+#include <common.h>
+#include <phy.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+
+u32 dpmac_to_devdisr[] = {
+	[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
+	[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
+	[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
+	[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
+	[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
+	[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
+	[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
+	[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
+	[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
+	[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
+	[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
+	[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
+	[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
+	[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
+	[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
+	[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
+	[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
+	[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
+};
+
+static int is_device_disabled(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 devdisr2 = in_le32(&gur->devdisr2);
+
+	return dpmac_to_devdisr[dpmac_id] & devdisr2;
+}
+
+void wriop_dpmac_disable(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+void wriop_dpmac_enable(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
+{
+	enum srds_prtcl;
+
+	if (is_device_disabled(dpmac_id + 1))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
+		return PHY_INTERFACE_MODE_SGMII;
+
+	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
+		return PHY_INTERFACE_MODE_25G_AUI;
+
+	if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
+		return PHY_INTERFACE_MODE_XLAUI;
+
+	if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
+		return PHY_INTERFACE_MODE_CAUI2;
+
+	if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
+		return PHY_INTERFACE_MODE_CAUI4;
+
+	return PHY_INTERFACE_MODE_NONE;
+}
+
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+void fsl_rgmii_init(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 ec;
+
+#ifdef CONFIG_SYS_FSL_EC1
+	ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
+		& FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
+	ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
+
+	if (!ec)
+		wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
+#endif
+
+#ifdef CONFIG_SYS_FSL_EC2
+	ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
+		& FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
+	ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
+
+	if (!ec)
+		wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
+#endif
+}
+#endif
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 7010bbc230..70d02d3f93 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -13,12 +13,15 @@
 #include <asm/io.h>
 #include <linux/immap_qe.h>
 #include <fsl_qe.h>
+#include <mmc.h>
+#include <environment.h>
+
 #ifdef CONFIG_ARCH_LS1021A
 #include <asm/arch/immap_ls102xa.h>
 #endif
-
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#include <mmc.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
 #endif
 
 #define MPC85xx_DEVDISR_QE_DISABLE	0x1
@@ -170,6 +173,33 @@ void qe_put_snum(u8 snum)
 	}
 }
 
+#ifdef CONFIG_TFABOOT
+void qe_init(uint qe_base)
+{
+	enum boot_src src = get_boot_src();
+
+	/* Init the QE IMMR base */
+	qe_immr = (qe_map_t *)qe_base;
+
+	if (src == BOOT_SOURCE_IFC_NOR) {
+		/*
+		 * Upload microcode to IRAM for those SOCs
+		 * which do not have ROM in QE.
+		 */
+		qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
+				   CONFIG_SYS_FSL_IFC_BASE));
+
+		/* enable the microcode in IRAM */
+		out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+	}
+
+	gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
+	gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
+
+	qe_sdma_init();
+	qe_snums_init();
+}
+#else
 void qe_init(uint qe_base)
 {
 	/* Init the QE IMMR base */
@@ -192,8 +222,53 @@ void qe_init(uint qe_base)
 	qe_snums_init();
 }
 #endif
+#endif
 
 #ifdef CONFIG_U_QE
+#ifdef CONFIG_TFABOOT
+void u_qe_init(void)
+{
+	enum boot_src src = get_boot_src();
+
+	qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
+
+	void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
+
+	if (src == BOOT_SOURCE_IFC_NOR)
+		addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE);
+
+	if (src == BOOT_SOURCE_QSPI_NOR)
+		addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE);
+
+	if (src == BOOT_SOURCE_SD_MMC) {
+		int dev = CONFIG_SYS_MMC_ENV_DEV;
+		u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+		u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
+
+		if (mmc_initialize(gd->bd)) {
+			printf("%s: mmc_initialize() failed\n", __func__);
+			return;
+		}
+		addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+		struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+		if (!mmc) {
+			free(addr);
+			printf("\nMMC cannot find device for ucode\n");
+		} else {
+			printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
+			       dev, blk, cnt);
+			mmc_init(mmc);
+			(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
+						addr);
+		}
+	}
+	if (!u_qe_upload_firmware(addr))
+		out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+	if (src == BOOT_SOURCE_SD_MMC)
+		free(addr);
+}
+#else
 void u_qe_init(void)
 {
 	qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
@@ -229,6 +304,7 @@ void u_qe_init(void)
 #endif
 }
 #endif
+#endif
 
 #ifdef CONFIG_U_QE
 void u_qe_resume(void)