Merge tag 'xilinx-for-v2020.01-part2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.01 part 2

common:
- Fix manual relocation for repeatable commands

arm:
- Also clean up generated dtbos

microblaze:
- Add support for Manual relocation in crypto framework
- Tune and align architecture bootm support

zynq:
- DT sync ups
- Some defconfig updates
- Remove empty board_early_init_f()

zynqmp:
- Clean firmware handing via drivers/firmware/
- DT/defconfig name alignments
- DT cleanups with using firmware based clock driver
- Some defconfig updates
- Add IIO ina226 DT description
- Tune zynqmp_psu_init_minimalize.sh script
- Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216

versal:
- Clean firmware handing via drivers/firmware/
- Add gpio support
- Enable DT overlay/USB/CLK/FPGA
- DT updates
- Tune mini configuration

spi:
- gqspi - Remove unused headers

9 files changed, 104 insertions, 25 deletions

diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index df87645774..7e97b0c4bf 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -12,6 +12,7 @@
 #include <clk.h>
 #include <dm.h>
 #include <asm/arch/sys_proto.h>
+#include <zynqmp_firmware.h>
 
 #define MAX_PARENT			100
 #define MAX_NODES			6
@@ -362,7 +363,7 @@ static u32 versal_clock_get_div(u32 clk_id)
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 	u32 div;
 
-	versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
 	div = ret_payload[1];
 
 	return div;
@@ -372,7 +373,7 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div)
 {
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
-	versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
 
 	return div;
 }
@@ -382,7 +383,7 @@ static u64 versal_clock_ref(u32 clk_id)
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 	int ref;
 
-	versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
 	ref = ret_payload[0];
 	if (!(ref & 1))
 		return ref_clk;
@@ -401,7 +402,7 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
 	u32 parent_rate, parent_id;
 	u32 id = clk_id & 0xFFF;
 
-	versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
 	res = ret_payload[1];
 	if (!res) {
 		printf("0%x PLL not enabled\n", clk_id);
@@ -411,9 +412,9 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
 	parent_id = clock[clock[id].parent[0].id].clk_id;
 	parent_rate = versal_clock_ref(parent_id);
 
-	versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
 	fbdiv = ret_payload[1];
-	versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
 	frac = ret_payload[1];
 
 	freq = (fbdiv * parent_rate) >> (1 << frac);
@@ -440,7 +441,7 @@ static u32 versal_clock_get_parentid(u32 clk_id)
 	u32 id = clk_id & 0xFFF;
 
 	if (versal_clock_mux(clk_id)) {
-		versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
+		xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
 				  ret_payload);
 		parent_id = ret_payload[1];
 	}
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 167f3f75a1..72fc39fa47 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -702,7 +702,6 @@ static struct clk_ops zynqmp_clk_ops = {
 
 static const struct udevice_id zynqmp_clk_ids[] = {
 	{ .compatible = "xlnx,zynqmp-clk" },
-	{ .compatible = "xlnx,zynqmp-clkc" },
 	{ }
 };
 
diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c
index 93deaa7f51..e91fe64458 100644
--- a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c
+++ b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c
@@ -13,10 +13,23 @@
 #include <asm/io.h>
 #include <linux/list.h>
 
+#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
 		struct key_prop *node, uint8_t *out)
 {
-	const struct mod_exp_ops *ops = device_get_ops(dev);
+	struct mod_exp_ops *ops = (struct mod_exp_ops *)device_get_ops(dev);
+
+#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
+	static bool done;
+
+	if (!done) {
+		done = true;
+		ops->mod_exp += gd->reloc_off;
+	}
+#endif
 
 	if (!ops->mod_exp)
 		return -ENOSYS;
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 15e82ac3b3..dea58b5581 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -7,10 +7,10 @@
 
 #include <common.h>
 #include <dm.h>
+#include <zynqmp_firmware.h>
 
 #if defined(CONFIG_ZYNQMP_IPI)
 #include <mailbox.h>
-#include <zynqmp_firmware.h>
 #include <asm/arch/sys_proto.h>
 
 #define PMUFW_PAYLOAD_ARG_CNT	8
@@ -54,7 +54,7 @@ static int send_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
 	if (IS_ENABLED(CONFIG_SPL_BUILD))
 		return ipi_req(req, req_len, res, res_maxlen);
 
-	return invoke_smc(req[0] + PM_SIP_SVC, 0, 0, 0, 0, res);
+	return xilinx_pm_request(req[0], 0, 0, 0, 0, res);
 }
 
 unsigned int zynqmp_firmware_version(void)
@@ -110,19 +110,19 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
 
 static int zynqmp_power_probe(struct udevice *dev)
 {
-	int ret = 0;
+	int ret;
 
 	debug("%s, (dev=%p)\n", __func__, dev);
 
 	ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan);
 	if (ret) {
-		debug("%s, cannot tx mailbox\n", __func__);
+		debug("%s: Cannot find tx mailbox\n", __func__);
 		return ret;
 	}
 
 	ret = mbox_get_by_name(dev, "rx", &zynqmp_power.rx_chan);
 	if (ret) {
-		debug("%s, cannot rx mailbox\n", __func__);
+		debug("%s: Cannot find rx mailbox\n", __func__);
 		return ret;
 	}
 
@@ -147,6 +147,37 @@ U_BOOT_DRIVER(zynqmp_power) = {
 };
 #endif
 
+int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+				     u32 arg3, u32 *ret_payload)
+{
+	/*
+	 * Added SIP service call Function Identifier
+	 * Make sure to stay in x0 register
+	 */
+	struct pt_regs regs;
+
+	if (current_el() == 3) {
+		printf("%s: Can't call SMC from EL3 context\n", __func__);
+		return -EPERM;
+	}
+
+	regs.regs[0] = PM_SIP_SVC | api_id;
+	regs.regs[1] = ((u64)arg1 << 32) | arg0;
+	regs.regs[2] = ((u64)arg3 << 32) | arg2;
+
+	smc_call(&regs);
+
+	if (ret_payload) {
+		ret_payload[0] = (u32)regs.regs[0];
+		ret_payload[1] = upper_32_bits(regs.regs[0]);
+		ret_payload[2] = (u32)regs.regs[1];
+		ret_payload[3] = upper_32_bits(regs.regs[1]);
+		ret_payload[4] = (u32)regs.regs[2];
+	}
+
+	return regs.regs[0];
+}
+
 static const struct udevice_id zynqmp_firmware_ids[] = {
 	{ .compatible = "xlnx,zynqmp-firmware" },
 	{ .compatible = "xlnx,versal-firmware"},
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index 69617a9b1d..4bcc213243 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -8,6 +8,7 @@
 #include <asm/arch/sys_proto.h>
 #include <memalign.h>
 #include <versalpl.h>
+#include <zynqmp_firmware.h>
 
 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
 {
@@ -38,7 +39,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
 	buf_lo = lower_32_bits(bin_buf);
 	buf_hi = upper_32_bits(bin_buf);
 
-	ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+	ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
 				buf_hi, 0, ret_payload);
 	if (ret)
 		puts("PL FPGA LOAD fail\n");
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index c2670271c8..d129b5459c 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -227,11 +227,12 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 	buf_hi = upper_32_bits(bin_buf);
 
 	if (xilfpga_old)
-		ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
-				 (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
+		ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+					buf_hi, (u32)(uintptr_t)bsizeptr,
+					bstype, ret_payload);
 	else
-		ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
-				 (u32)bsize, 0, ret_payload);
+		ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+					buf_hi, (u32)bsize, 0, ret_payload);
 
 	if (ret)
 		puts("PL FPGA LOAD fail\n");
@@ -272,7 +273,8 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
 	buf_lo = lower_32_bits((ulong)buf);
 	buf_hi = upper_32_bits((ulong)buf);
 
-	ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+	ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+				buf_hi,
 			 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
 			 flag, ret_payload);
 	if (ret)
@@ -289,8 +291,8 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
 	int ret;
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
-	ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
-			 0, ret_payload);
+	ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
+				0, ret_payload);
 	if (!ret)
 		printf("PCAP status\t0x%x\n", ret_payload[1]);
 
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 39f2c7e328..c1ad5d64a3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -301,7 +301,7 @@ config MVEBU_GPIO
 
 config ZYNQ_GPIO
 	bool "Zynq GPIO driver"
-	depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP)
+	depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL)
 	default y
 	help
 	  Supports GPIO access on Zynq SoC.
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index a760c5bdda..fe3b2c3b1a 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -93,6 +93,9 @@
 /* GPIO upper 16 bit mask */
 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
 
+#define PMC_GPIO_NR_GPIOS	116
+#define PMC_GPIO_MAX_BANK	5
+
 struct zynq_gpio_platdata {
 	phys_addr_t base;
 	const struct zynq_platform_data *p_data;
@@ -114,6 +117,33 @@ struct zynq_platform_data {
 	u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
 };
 
+#define VERSAL_GPIO_NR_GPIOS	58
+#define VERSAL_GPIO_MAX_BANK	4
+
+static const struct zynq_platform_data versal_gpio_def = {
+	.label = "versal_gpio",
+	.ngpio = VERSAL_GPIO_NR_GPIOS,
+	.max_bank = VERSAL_GPIO_MAX_BANK,
+	.bank_min[0] = 0,
+	.bank_max[0] = 25,
+	.bank_min[3] = 26,
+	.bank_max[3] = 57,
+};
+
+static const struct zynq_platform_data pmc_gpio_def = {
+	.label = "pmc_gpio",
+	.ngpio = PMC_GPIO_NR_GPIOS,
+	.max_bank = PMC_GPIO_MAX_BANK,
+	.bank_min[0] = 0,
+	.bank_max[0] = 25,
+	.bank_min[1] = 26,
+	.bank_max[1] = 51,
+	.bank_min[3] = 52,
+	.bank_max[3] = 83,
+	.bank_min[4] = 84,
+	.bank_max[4] = 115,
+};
+
 static const struct zynq_platform_data zynqmp_gpio_def = {
 	.label = "zynqmp_gpio",
 	.ngpio = ZYNQMP_GPIO_NR_GPIOS,
@@ -329,6 +359,10 @@ static const struct udevice_id zynq_gpio_ids[] = {
 	  .data = (ulong)&zynq_gpio_def},
 	{ .compatible = "xlnx,zynqmp-gpio-1.0",
 	  .data = (ulong)&zynqmp_gpio_def},
+	{ .compatible = "xlnx,versal-gpio-1.0",
+	  .data = (ulong)&versal_gpio_def},
+	{ .compatible = "xlnx,pmc-gpio-1.0",
+	  .data = (ulong)&pmc_gpio_def },
 	{ }
 };
 
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 04ea42cbcc..c11f040200 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -6,8 +6,6 @@
  */
 
 #include <common.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <clk.h>