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authorDavid Sniatkiwicz <davidsn@marvell.com>2018-08-29 11:56:18 +0300
committerStefan Roese <sr@denx.de>2018-09-19 09:02:34 +0200
commite76afd84095a10e7cd9d8ee6b74ed94941e5f4f8 (patch)
treea04053c6aa9845804b346ccf1759fbfe0de703db /drivers
parentb7b3f2c8bbf346b29f877b61d7e2b12a877b01d0 (diff)
fix: nand: pxa3xx: Add WA for eliminating flash ready timeout
add delay before processing the status flags in pxa3xx_nand_irq(). Signed-off-by: David Sniatkiwicz <davidsn@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> c: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 3323557999..2a02a9d58e 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -668,6 +668,9 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
cmd_done = NDSR_CS1_CMDD;
}
+ /* TODO - find out why we need the delay during write operation. */
+ ndelay(1);
+
status = nand_readl(info, NDSR);
if (status & NDSR_UNCORERR)