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authorKoen Vandeputte <koen.vandeputte@ncentric.com>2018-01-04 14:54:34 +0100
committerStefano Babic <sbabic@denx.de>2018-01-12 14:28:04 +0100
commitf57263ee9bb8b5d9f39b48d09d21114c9dbb6a02 (patch)
tree41e8d456a156b5d1f123eb89f7970cfeb92e4eda /drivers
parent0f194018f2b431ce81606c2b6be7c8992d09c749 (diff)
drivers: pci: imx: fix enumeration logic error
By default, the subordinate is set equally to the secondary bus (1) when the RC boots, and does not alter afterwards. This means that theoretically, the highest bus reachable downstream is bus 1. Force the PCIe RC subordinate to 0xff, otherwise no downstream devices will be detected behind bus 1 if the booting OS does not allow enumerating a higher busnr than the subordinate value of the primary bus. Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pcie_imx.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 90a34063b0..ef66a1d3f4 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -616,6 +616,17 @@ static int imx_pcie_link_up(void)
imx_pcie_regions_setup();
/*
+ * By default, the subordinate is set equally to the secondary
+ * bus (0x01) when the RC boots.
+ * This means that theoretically, only bus 1 is reachable from the RC.
+ * Force the PCIe RC subordinate to 0xff, otherwise no downstream
+ * devices will be detected if the enumeration is applied strictly.
+ */
+ tmp = readl(MX6_DBI_ADDR + 0x18);
+ tmp |= (0xff << 16);
+ writel(tmp, MX6_DBI_ADDR + 0x18);
+
+ /*
* FIXME: Force the PCIe RC to Gen1 operation
* The RC must be forced into Gen1 mode before bringing the link
* up, otherwise no downstream devices are detected. After the