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| author | Rick Chen <rick@andestech.com> | 2018-05-30 16:12:19 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-05-30 16:21:30 +0800 |
| commit | 6ffea11b89099d72029bc644f7664736ee7ca667 (patch) | |
| tree | 1ad86340c97ff790a4414d5af2a5fecf20695f30 /fs/fs.c | |
| parent | 9171ab8836511ab1e65e120b7288acd6d5baac70 (diff) | |
travis.yml: Support RISC-V 64-bit
Fix riscv: ax25-ae350 build fail problem
https://travis-ci.org/trini/u-boot/jobs/385147373
...
Building current source for 1 boards (1 thread, 2 jobs per thread)
riscv: + ax25-ae350
+arch/riscv/cpu/ax25/start.S: Assembler messages:
+arch/riscv/cpu/ax25/start.S:48: Error: unrecognized opcode `sd a2,0(t0)'
+arch/riscv/cpu/ax25/start.S:112: Error: unrecognized opcode `ld t5,0(t0)'
...
After apply the commit
configs: ax25-ae350: Set 64-bit as default configuration
Toolchain shall be also setuped with 64-bit in .travis.yml.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Chih-Mao Chen <cmchen@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
Diffstat (limited to 'fs/fs.c')
0 files changed, 0 insertions, 0 deletions