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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-04-30 16:30:21 +0200 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-05-14 09:02:12 +0200 |
| commit | dc7e5f190de5ac89fafe3e6212a6167a2b7a36d0 (patch) | |
| tree | 7ecbf62873a7a19b8327a392fcd9593b3ab7effb /fs/yaffs2/yaffs_qsort.c | |
| parent | 7e8471cae5c6614c54b9cfae2746d7299bd47a0c (diff) | |
arm: stm32mp: activate data cache on DDR in SPL
Activate cache on DDR to improve the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START
Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the data cache
and the TLB.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'fs/yaffs2/yaffs_qsort.c')
0 files changed, 0 insertions, 0 deletions