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authorMichal Simek <michal.simek@xilinx.com>2018-06-14 09:43:34 +0200
committerMichal Simek <michal.simek@xilinx.com>2018-06-15 08:54:05 +0200
commite90d2659e46ab9483c24e08611c06922a8ec25d4 (patch)
tree7f163cb75a279c0fbfc8d4310a8d90d2660ae2e0 /include/.gitignore
parentc9a2c47b91b0334e7c7f5aaa0421ba7d751edbef (diff)
serial: zynq: Write chars till output fifo is full
Change logic and put char to fifo till there is a space in output fifo. Origin logic was that output fifo needs to be empty. It means only one char was in output queue. Also remove unused ZYNQ_UART_SR_TXEMPTY macro. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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