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authorSimon Glass <sjg@chromium.org>2020-07-07 13:12:01 -0600
committerBin Meng <bmeng.cn@gmail.com>2020-07-17 14:32:24 +0800
commitf8054dd8ba533be0e2ebd7965b95446a1f573953 (patch)
tree3236d3b0505cb448f60289636a53643ee538a3a3 /include/acpi
parentf9189d5ada8d48932463dc1d56ea4d44c050ebbd (diff)
acpi: Add support for writing a GPIO power sequence
Power to some devices is controlled by GPIOs. Add a way to generate ACPI code to enable and disable a GPIO so that this can be handled within an ACPI method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'include/acpi')
-rw-r--r--include/acpi/acpigen.h56
1 files changed, 56 insertions, 0 deletions
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 2c07a56208..d06d2c0c73 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -13,6 +13,7 @@
#include <linux/types.h>
struct acpi_ctx;
+struct acpi_gpio;
/* Top 4 bits of the value used to indicate a three-byte length value */
#define ACPI_PKG_LEN_3_BYTES 0x80
@@ -343,4 +344,59 @@ void acpigen_write_power_res(struct acpi_ctx *ctx, const char *name, uint level,
uint order, const char *const dev_states[],
size_t dev_states_count);
+/**
+ * acpigen_set_enable_tx_gpio() - Emit ACPI code to enable/disable a GPIO
+ *
+ * This emits code to either enable to disable a Tx GPIO. It takes account of
+ * the GPIO polarity.
+ *
+ * The code needs access to the DW0 register for the pad being used. This is
+ * provided by gpio->pin0_addr and ACPI methods must be defined for the board
+ * which can read and write the pad's DW0 register given this address:
+ * @dw0_read: takes a single argument, the DW0 address
+ * returns the DW0 value
+ * @dw0:write: takes two arguments, the DW0 address and the value to write
+ * no return value
+ *
+ * Example code (-- means comment):
+ *
+ * -- Get Pad Configuration DW0 register value
+ * Method (GPC0, 0x1, Serialized)
+ * {
+ * -- Arg0 - GPIO DW0 address
+ * Store (Arg0, Local0)
+ * OperationRegion (PDW0, SystemMemory, Local0, 4)
+ * Field (PDW0, AnyAcc, NoLock, Preserve) {
+ * TEMP, 32
+ * }
+ * Return (TEMP)
+ * }
+ *
+ * -- Set Pad Configuration DW0 register value
+ * Method (SPC0, 0x2, Serialized)
+ * {
+ * -- Arg0 - GPIO DW0 address
+ * -- Arg1 - Value for DW0 register
+ * Store (Arg0, Local0)
+ * OperationRegion (PDW0, SystemMemory, Local0, 4)
+ * Field (PDW0, AnyAcc, NoLock, Preserve) {
+ * TEMP,32
+ * }
+ * Store (Arg1, TEMP)
+ * }
+ *
+ *
+ * @ctx: ACPI context pointer
+ * @tx_state_val: Mask to use to toggle the TX state on the GPIO pin, e,g.
+ * PAD_CFG0_TX_STATE
+ * @dw0_read: Method name to use to read dw0, e.g. "\\_SB.GPC0"
+ * @dw0_write: Method name to use to read dw0, e.g. "\\_SB.SPC0"
+ * @gpio: GPIO to change
+ * @enable: true to enable GPIO, false to disable
+ * Returns 0 on success, -ve on error.
+ */
+int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32 tx_state_val,
+ const char *dw0_read, const char *dw0_write,
+ struct acpi_gpio *gpio, bool enable);
+
#endif