punt Blackfin VDSP headers and import sanitized/auto-generated ones

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

25 files changed, 36330 insertions, 0 deletions

diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
new file mode 100644
index 0000000000..e9572a0b00
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
@@ -0,0 +1,4381 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF542_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
+#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
+#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
+#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
+#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
+#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
+#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
+#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
+#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
+#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
+#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
+#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
+#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
+#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
+#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
+#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
+#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
+#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
+#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
+#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
+#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
+#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
+#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
+#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
+#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
+#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
+#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
+#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
+#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
+#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
+#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
+#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
+#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
+#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
+#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
+#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
+#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
+#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
+#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
+#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
+#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
+#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
+#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
+#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
+#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
+#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
+#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
+#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
+#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
+#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
+#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
+#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
+#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
+#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
+#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
+#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
+#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
+#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
+#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
+#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
+#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
+#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
+#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
+#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
+#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
+#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
+#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
+#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
+#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
+#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
+#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
+#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
+#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
+#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
+#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
+#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
+#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
+#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
+#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
+#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
+#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
+#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
+#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
+#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
+#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
+#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
+#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
+#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
+#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
+#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
+#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
+#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
+#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
+#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
+#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
+#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
+#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
+#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
+#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
+#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
+#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
+#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
+#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
+#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
+#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
+#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
+#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
+#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
+#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
+#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
+#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
+#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
+#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
+#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
+#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
+#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
+#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
+#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
+#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
+#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
+#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
+#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
+#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
+#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
+#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
+#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
+#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
+#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
+#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
+#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
+#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
+#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
+#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
+#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
+#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
+#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
+#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
+#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
+#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
+#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
+#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
+#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
+#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
+#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
+#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
+#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
+#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
+#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
+#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
+#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
+#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
+#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
+#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
+#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
+#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
+#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
+#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
+#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
+#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
+#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
+#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
+#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
+#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
+#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
+#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
+#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
+#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
+#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
+#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
+#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
+#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
+#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
+#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
+#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
+#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
+#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
+#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
+#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
+#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
+#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
+#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
+#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
+#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
+#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
+#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
+#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
+#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
+#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
+#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
+#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
+#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
+#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
+#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
+#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
+#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
+#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
+#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
+#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
+#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
+#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
+#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
+#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
+#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
+#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
+#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
+#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
+#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
+#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
+#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
+#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
+#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
+#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
+#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
+#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
+#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
+#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
+#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
+#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
+#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
+#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
+#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
+#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
+#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
+#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
+#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
+#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
+#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
+#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
+#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
+#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
+#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
+#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
+#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
+#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
+#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
+#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
+#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
+#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
+#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
+#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
+#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
+#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
+#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
+#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
+#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
+#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
+#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
+#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
+#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
+#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
+#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
+#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
+#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
+#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
+#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
+#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
+#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
+#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
+#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
+#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
+#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
+#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
+#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
+#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
+#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
+#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
+#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
+#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
+#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
+#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
+#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
+#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
+#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
+#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
+#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
+#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
+#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
+#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
+#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
+#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
+#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
+#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
+#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
+#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
+#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
+#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
+#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
+#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
+#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
+#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
+#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
+#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
+#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
+#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
+#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
+#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
+#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
+#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
+#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
+#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
+#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
+#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
+#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
+#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
+#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
+#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
+#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
+#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
+#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
+#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
+#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
+#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
+#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
+#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
+#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
+#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
+#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
+#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
+#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
+#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
+#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
+#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
+#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
+#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
+#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
+#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
+#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
+#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
+#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
+#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
+#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
+#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
+#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
+#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
+#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
+#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
+#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
+#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
+#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
+#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
+#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
+#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
+#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
+#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
+#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
+#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
+#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
+#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
+#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
+#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
+#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
+#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
+#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
+#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
+#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
+#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
+#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
+#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
+#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
+#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
+#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
+#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
+#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
+#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
+#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
+#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
+#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
+#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
+#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
+#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
+#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
+#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
+#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
+#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
+#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
+#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
+#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
+#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
+#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
+#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
+#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
+#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
+#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
+#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
+#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
+#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
+#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
+#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
+#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
+#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
+#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
+#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
+#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
+#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
+#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
+#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
+#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
+#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
+#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
+#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
+#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
+#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
+#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
+#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
+#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
+#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
+#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
+#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
+#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
+#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
+#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
+#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
+#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
+#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
+#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
+#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
+#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
+#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
+#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
+#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
+#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
+#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
+#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
+#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
+#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
+#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
+#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
+#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
+#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
+#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
+#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
+#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
+#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
+#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
+#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
+#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
+#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
+#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
+#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
+#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
+#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
+#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
+#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
+#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
+#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
+#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
+#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
+#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
+#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
+#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
+#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
+#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
+#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
+#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
+#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
+#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
+#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
+#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
+#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
+#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
+#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
+#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
+#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
+#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
+#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
+#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
+#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
+#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
+#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
+#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
+#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
+#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
+#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
+#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
+#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
+#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
+#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_read_SPORT2_TX()          bfin_read32(SPORT2_TX)
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_read_SPORT3_TX()          bfin_read32(SPORT3_TX)
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF542_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_def.h
new file mode 100644
index 0000000000..f294a850ab
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_def.h
@@ -0,0 +1,1467 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF542_extended__
+#define __BFIN_DEF_ADSP_EDN_BF542_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
+#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
+#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+#define USB_FADDR                      0xFFC03C00 /* Function address register */
+#define USB_POWER                      0xFFC03C04 /* Power management register */
+#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03C20 /* USB frame number */
+#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF542_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
new file mode 100644
index 0000000000..968cd3eb3a
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
@@ -0,0 +1,4975 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF544_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
+#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
+#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
+#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
+#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
+#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
+#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
+#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
+#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
+#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
+#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
+#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
+#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
+#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
+#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
+#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
+#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
+#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
+#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
+#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
+#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
+#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
+#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
+#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
+#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
+#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
+#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
+#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
+#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
+#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
+#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
+#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
+#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
+#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
+#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
+#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
+#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
+#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
+#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
+#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
+#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
+#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
+#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
+#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
+#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
+#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
+#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
+#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
+#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
+#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
+#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
+#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
+#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
+#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
+#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
+#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
+#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
+#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
+#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
+#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
+#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
+#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
+#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
+#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
+#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
+#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
+#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
+#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
+#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
+#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
+#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
+#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
+#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
+#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
+#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
+#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
+#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
+#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
+#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
+#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
+#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
+#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
+#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
+#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
+#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
+#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
+#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
+#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
+#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
+#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
+#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
+#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
+#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
+#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
+#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
+#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
+#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
+#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
+#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
+#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
+#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
+#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
+#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
+#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
+#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
+#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
+#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
+#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
+#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
+#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
+#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
+#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
+#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
+#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
+#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
+#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
+#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
+#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
+#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
+#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
+#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
+#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
+#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
+#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
+#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
+#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
+#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
+#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
+#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
+#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
+#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
+#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
+#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
+#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
+#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
+#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
+#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
+#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
+#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
+#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
+#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
+#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
+#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
+#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
+#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
+#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
+#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
+#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
+#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
+#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
+#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
+#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
+#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
+#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
+#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
+#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
+#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
+#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
+#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
+#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
+#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
+#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
+#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
+#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
+#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
+#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
+#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
+#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
+#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
+#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
+#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
+#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
+#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
+#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
+#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
+#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
+#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
+#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
+#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
+#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
+#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
+#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
+#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
+#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
+#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
+#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
+#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
+#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
+#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
+#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
+#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
+#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
+#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
+#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
+#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
+#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
+#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
+#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
+#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
+#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
+#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
+#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
+#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
+#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
+#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
+#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
+#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
+#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
+#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
+#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
+#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
+#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
+#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
+#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
+#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
+#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
+#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
+#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
+#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
+#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
+#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
+#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
+#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
+#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
+#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
+#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
+#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
+#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
+#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
+#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
+#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
+#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
+#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
+#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
+#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
+#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
+#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
+#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
+#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
+#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
+#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
+#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
+#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
+#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
+#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
+#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
+#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
+#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
+#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
+#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
+#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
+#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
+#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
+#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
+#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
+#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
+#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
+#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
+#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
+#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
+#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
+#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
+#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
+#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
+#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
+#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
+#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
+#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
+#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
+#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
+#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
+#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
+#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
+#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
+#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
+#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
+#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
+#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
+#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
+#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
+#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
+#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
+#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
+#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
+#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
+#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
+#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
+#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
+#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
+#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
+#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
+#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
+#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
+#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
+#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
+#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
+#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
+#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
+#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
+#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
+#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
+#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
+#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
+#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
+#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
+#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
+#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
+#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
+#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
+#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
+#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
+#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
+#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
+#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
+#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
+#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
+#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
+#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
+#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
+#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
+#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
+#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
+#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
+#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
+#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
+#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
+#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
+#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
+#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
+#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
+#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
+#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
+#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
+#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
+#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
+#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
+#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
+#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
+#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
+#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
+#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
+#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
+#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
+#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
+#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
+#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
+#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
+#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
+#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
+#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
+#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
+#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
+#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
+#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
+#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
+#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
+#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
+#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
+#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
+#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
+#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
+#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
+#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
+#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
+#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
+#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
+#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
+#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
+#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
+#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
+#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
+#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
+#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
+#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
+#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
+#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
+#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
+#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
+#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
+#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
+#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
+#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
+#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
+#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
+#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
+#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
+#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
+#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
+#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
+#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
+#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
+#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
+#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
+#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
+#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
+#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
+#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
+#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
+#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
+#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
+#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
+#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
+#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
+#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
+#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
+#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
+#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
+#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
+#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
+#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
+#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
+#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
+#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
+#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
+#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
+#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
+#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
+#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
+#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
+#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
+#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
+#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
+#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
+#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
+#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
+#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
+#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
+#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
+#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
+#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
+#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
+#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
+#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
+#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
+#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
+#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
+#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
+#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
+#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
+#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
+#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
+#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
+#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
+#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
+#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
+#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
+#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
+#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
+#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
+#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
+#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
+#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
+#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
+#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
+#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
+#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
+#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
+#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
+#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
+#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
+#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
+#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
+#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
+#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
+#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
+#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
+#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
+#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
+#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
+#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
+#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
+#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
+#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
+#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
+#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
+#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
+#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
+#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
+#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
+#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
+#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
+#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
+#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
+#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
+#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
+#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
+#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
+#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
+#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
+#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
+#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
+#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
+#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
+#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
+#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
+#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
+#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
+#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
+#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
+#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
+#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
+#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
+#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
+#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
+#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
+#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
+#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
+#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
+#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
+#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
+#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
+#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
+#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
+#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
+#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
+#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
+#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
+#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
+#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
+#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
+#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
+#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
+#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
+#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
+#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
+#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
+#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
+#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
+#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
+#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
+#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
+#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
+#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
+#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
+#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
+#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
+#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
+#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
+#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
+#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
+#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
+#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
+#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
+#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
+#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
+#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
+#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
+#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
+#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
+#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
+#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
+#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
+#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
+#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
+#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
+#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
+#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
+#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
+#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
+#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
+#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
+#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
+#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
+#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
+#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
+#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
+#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
+#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
+#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
+#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
+#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
+#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
+#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
+#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
+#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
+#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
+#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
+#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
+#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
+#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
+#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
+#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
+#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
+#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
+#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
+#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
+#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
+#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
+#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
+#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
+#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
+#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
+#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
+#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
+#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
+#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
+#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
+#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
+#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
+#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
+#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
+#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
+#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
+#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
+#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
+#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
+#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
+#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
+#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
+#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
+#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
+#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
+#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
+#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
+#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
+#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
+#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
+#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
+#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
+#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
+#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
+#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
+#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
+#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
+#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
+#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
+#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
+#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
+#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
+#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
+#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
+#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
+#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
+#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
+#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
+#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
+#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
+#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
+#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
+#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
+#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
+#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
+#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
+#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
+#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
+#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
+#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
+#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
+#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
+#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
+#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
+#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
+#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
+#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
+#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
+#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
+#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
+#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
+#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
+#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
+#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
+#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
+#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
+#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
+#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
+#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
+#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
+#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
+#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
+#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
+#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
+#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
+#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
+#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
+#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
+#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
+#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
+#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
+#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
+#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
+#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
+#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
+#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
+#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
+#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
+#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
+#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
+#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
+#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
+#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
+#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
+#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
+#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
+#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
+#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
+#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
+#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
+#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
+#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
+#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
+#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
+#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
+#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
+#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
+#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
+#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
+#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
+#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
+#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
+#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
+#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
+#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
+#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
+#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
+#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
+#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
+#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
+#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
+#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
+#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
+#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
+#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
+#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
+#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
+#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
+#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
+#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
+#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
+#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
+#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
+#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
+#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
+#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
+#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
+#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
+#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
+#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
+#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
+#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
+#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
+#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
+#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
+#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
+#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
+#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
+#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
+#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
+#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
+#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
+#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
+#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
+#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
+#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
+#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
+#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
+#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
+#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
+#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
+#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
+#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
+#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
+#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
+#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
+#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
+#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
+#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
+#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
+#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
+#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
+#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
+#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
+#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
+#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
+#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
+#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
+#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
+#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
+#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
+#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
+#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
+#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
+#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
+#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
+#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
+#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
+#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
+#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
+#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
+#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
+#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
+#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
+#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
+#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
+#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
+#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
+#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
+#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
+#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
+#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
+#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
+#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
+#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
+#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
+#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
+#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
+#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
+#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
+#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
+#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
+#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
+#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
+#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
+#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
+#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
+#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
+#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
+#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
+#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
+#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
+#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_read_SPORT2_TX()          bfin_read32(SPORT2_TX)
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_read_SPORT3_TX()          bfin_read32(SPORT3_TX)
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF544_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_def.h
new file mode 100644
index 0000000000..3c14d22d56
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_def.h
@@ -0,0 +1,1665 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF544_extended__
+#define __BFIN_DEF_ADSP_EDN_BF544_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
+#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
+#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
+#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
+#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
+#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
+#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
+#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
+#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
+#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF544_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
new file mode 100644
index 0000000000..bd40f356e8
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
@@ -0,0 +1,3619 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF547_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF547_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
+#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
+#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
+#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
+#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
+#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
+#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
+#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
+#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
+#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
+#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
+#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
+#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
+#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
+#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
+#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
+#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
+#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
+#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
+#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
+#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
+#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
+#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
+#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
+#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
+#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
+#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
+#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
+#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
+#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
+#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
+#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
+#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
+#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
+#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
+#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
+#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
+#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
+#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
+#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
+#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
+#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
+#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
+#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
+#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
+#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
+#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
+#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
+#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
+#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
+#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
+#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
+#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
+#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
+#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
+#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
+#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
+#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
+#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
+#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
+#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
+#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
+#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
+#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
+#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
+#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
+#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
+#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
+#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
+#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
+#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
+#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
+#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
+#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
+#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
+#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
+#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
+#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
+#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
+#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
+#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
+#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
+#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
+#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
+#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
+#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
+#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
+#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
+#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
+#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
+#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
+#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
+#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
+#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
+#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
+#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
+#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
+#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
+#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
+#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
+#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
+#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
+#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
+#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
+#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
+#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
+#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
+#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
+#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
+#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
+#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
+#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
+#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
+#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
+#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
+#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
+#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
+#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
+#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
+#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
+#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
+#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
+#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
+#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
+#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
+#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
+#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
+#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
+#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
+#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
+#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
+#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
+#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
+#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
+#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
+#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
+#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
+#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
+#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
+#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
+#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
+#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
+#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
+#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
+#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
+#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
+#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
+#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
+#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
+#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
+#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
+#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
+#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
+#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
+#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
+#define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_read_SPORT2_TX()          bfin_read32(SPORT2_TX)
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_read_SPORT3_TX()          bfin_read32(SPORT3_TX)
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
+#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
+#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
+#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
+#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
+#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
+#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
+#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
+#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
+#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
+#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
+#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
+#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
+#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
+#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
+#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
+#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
+#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
+#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
+#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
+#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF547_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_def.h
new file mode 100644
index 0000000000..0e482792cf
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_def.h
@@ -0,0 +1,1213 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF547_extended__
+#define __BFIN_DEF_ADSP_EDN_BF547_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
+#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
+#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
+#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
+#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
+#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
+#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
+#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
+#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
+#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
+#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
+#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
+#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
+#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
+#define UART2_LCR                      0xFFC0210C /* Line Control Register */
+#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
+#define UART2_LSR                      0xFFC02114 /* Line Status Register */
+#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
+#define UART2_SCR                      0xFFC0211C /* Scratch Register */
+#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
+#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
+#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+#define USB_FADDR                      0xFFC03C00 /* Function address register */
+#define USB_POWER                      0xFFC03C04 /* Power management register */
+#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03C20 /* USB frame number */
+#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF547_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
new file mode 100644
index 0000000000..77cd5dc779
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
@@ -0,0 +1,5791 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF548_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF548_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
+#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
+#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
+#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
+#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
+#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
+#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
+#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
+#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
+#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
+#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
+#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
+#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
+#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
+#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
+#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
+#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
+#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
+#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
+#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
+#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
+#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
+#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
+#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
+#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
+#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
+#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
+#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
+#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
+#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
+#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
+#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
+#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
+#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
+#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
+#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
+#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
+#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
+#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
+#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
+#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
+#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
+#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
+#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
+#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
+#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
+#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
+#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
+#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
+#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
+#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
+#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
+#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
+#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
+#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
+#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
+#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
+#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
+#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
+#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
+#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
+#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
+#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
+#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
+#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
+#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
+#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
+#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
+#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
+#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
+#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
+#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
+#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
+#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
+#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
+#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
+#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
+#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
+#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
+#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
+#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
+#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
+#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
+#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
+#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
+#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
+#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
+#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
+#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
+#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
+#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
+#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
+#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
+#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
+#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
+#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
+#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
+#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
+#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
+#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
+#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
+#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
+#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
+#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
+#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
+#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
+#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
+#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
+#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
+#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
+#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
+#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
+#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
+#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
+#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
+#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
+#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
+#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
+#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
+#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
+#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
+#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
+#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
+#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
+#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
+#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
+#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
+#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
+#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
+#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
+#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
+#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
+#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
+#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
+#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
+#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
+#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
+#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
+#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
+#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
+#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
+#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
+#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
+#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
+#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
+#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
+#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
+#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
+#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
+#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
+#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
+#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
+#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
+#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
+#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
+#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
+#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
+#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
+#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
+#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
+#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
+#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
+#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
+#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
+#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
+#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
+#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
+#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
+#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
+#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
+#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
+#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
+#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
+#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
+#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
+#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
+#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
+#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
+#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
+#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
+#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
+#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
+#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
+#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
+#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
+#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
+#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
+#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
+#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
+#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
+#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
+#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
+#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
+#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
+#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
+#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
+#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
+#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
+#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
+#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
+#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
+#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
+#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
+#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
+#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
+#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
+#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
+#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
+#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
+#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
+#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
+#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
+#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
+#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
+#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
+#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
+#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
+#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
+#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
+#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
+#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
+#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
+#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
+#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
+#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
+#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
+#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
+#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
+#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
+#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
+#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
+#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
+#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
+#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
+#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
+#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
+#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
+#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
+#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
+#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
+#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
+#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
+#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
+#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
+#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
+#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
+#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
+#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
+#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
+#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
+#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
+#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
+#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
+#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
+#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
+#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
+#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
+#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
+#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
+#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
+#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
+#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
+#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
+#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
+#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
+#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
+#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
+#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
+#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
+#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
+#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
+#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
+#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
+#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
+#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
+#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
+#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
+#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
+#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
+#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
+#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
+#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
+#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
+#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
+#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
+#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
+#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
+#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
+#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
+#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
+#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
+#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
+#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
+#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
+#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
+#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
+#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
+#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
+#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
+#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
+#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
+#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
+#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
+#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
+#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
+#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
+#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
+#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
+#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
+#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
+#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
+#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
+#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
+#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
+#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
+#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
+#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
+#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
+#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
+#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
+#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
+#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
+#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
+#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
+#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
+#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
+#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
+#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
+#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
+#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
+#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
+#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
+#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
+#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
+#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
+#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
+#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
+#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
+#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
+#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
+#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
+#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
+#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
+#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
+#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
+#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
+#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
+#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
+#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
+#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
+#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
+#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
+#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
+#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
+#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
+#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
+#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
+#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
+#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
+#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
+#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
+#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
+#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
+#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
+#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
+#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
+#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
+#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
+#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
+#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
+#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
+#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
+#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
+#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
+#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
+#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
+#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
+#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
+#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
+#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
+#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
+#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
+#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
+#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
+#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
+#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
+#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
+#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
+#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
+#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
+#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
+#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
+#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
+#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
+#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
+#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
+#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
+#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
+#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
+#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
+#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
+#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
+#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
+#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
+#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
+#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
+#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
+#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
+#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
+#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
+#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
+#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
+#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
+#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
+#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
+#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
+#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
+#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
+#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
+#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
+#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
+#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
+#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
+#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
+#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
+#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
+#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
+#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
+#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
+#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
+#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
+#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
+#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
+#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
+#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
+#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
+#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
+#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
+#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
+#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
+#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
+#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
+#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
+#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
+#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
+#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
+#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
+#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
+#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
+#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
+#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
+#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
+#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
+#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
+#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
+#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
+#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
+#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
+#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
+#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
+#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
+#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
+#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
+#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
+#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
+#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
+#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
+#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
+#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
+#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
+#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
+#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
+#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
+#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
+#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
+#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
+#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
+#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
+#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
+#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
+#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
+#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
+#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
+#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
+#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
+#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
+#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
+#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
+#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
+#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
+#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
+#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
+#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
+#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
+#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
+#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
+#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
+#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
+#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
+#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
+#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
+#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
+#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
+#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
+#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
+#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
+#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
+#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
+#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
+#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
+#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
+#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
+#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
+#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
+#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
+#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
+#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
+#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
+#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
+#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
+#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
+#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
+#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
+#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
+#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
+#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
+#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
+#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
+#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
+#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
+#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
+#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
+#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
+#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
+#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
+#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
+#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
+#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
+#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
+#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
+#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
+#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
+#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
+#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
+#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
+#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
+#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
+#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
+#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
+#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
+#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
+#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
+#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
+#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
+#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
+#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
+#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
+#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
+#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
+#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
+#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
+#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
+#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
+#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
+#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
+#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
+#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
+#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
+#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
+#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
+#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
+#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
+#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
+#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
+#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
+#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
+#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
+#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
+#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
+#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
+#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
+#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
+#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
+#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
+#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
+#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
+#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
+#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
+#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
+#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
+#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
+#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
+#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
+#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
+#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
+#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
+#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
+#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
+#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
+#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
+#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
+#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
+#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
+#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
+#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
+#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
+#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
+#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
+#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
+#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
+#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
+#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
+#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
+#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
+#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
+#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
+#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
+#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
+#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
+#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
+#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
+#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
+#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
+#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
+#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
+#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
+#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
+#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
+#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
+#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
+#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
+#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
+#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
+#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
+#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
+#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
+#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
+#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
+#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
+#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
+#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
+#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
+#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
+#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
+#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
+#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
+#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
+#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
+#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
+#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
+#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
+#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
+#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
+#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
+#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
+#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
+#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
+#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
+#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
+#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
+#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
+#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
+#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
+#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
+#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
+#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
+#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
+#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
+#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
+#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
+#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
+#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
+#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
+#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
+#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
+#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
+#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
+#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
+#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
+#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
+#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
+#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
+#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
+#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
+#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
+#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
+#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
+#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
+#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
+#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
+#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
+#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
+#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
+#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
+#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
+#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
+#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
+#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
+#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
+#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
+#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
+#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
+#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
+#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
+#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
+#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
+#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
+#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
+#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
+#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
+#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
+#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
+#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
+#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
+#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
+#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
+#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
+#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
+#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
+#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
+#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
+#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
+#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
+#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
+#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
+#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
+#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
+#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
+#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
+#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
+#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
+#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
+#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
+#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
+#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
+#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
+#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
+#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
+#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
+#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
+#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
+#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
+#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
+#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
+#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
+#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
+#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
+#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
+#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
+#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
+#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
+#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
+#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
+#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
+#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
+#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
+#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
+#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
+#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
+#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
+#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
+#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
+#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
+#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
+#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
+#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
+#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
+#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
+#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
+#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
+#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
+#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
+#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
+#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
+#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
+#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
+#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
+#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
+#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
+#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
+#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
+#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
+#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
+#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
+#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
+#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
+#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
+#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
+#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
+#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
+#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
+#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
+#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
+#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
+#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
+#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
+#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
+#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
+#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
+#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
+#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
+#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
+#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
+#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
+#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
+#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
+#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
+#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
+#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
+#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
+#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
+#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
+#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
+#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
+#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
+#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
+#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
+#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
+#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
+#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
+#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
+#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
+#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
+#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
+#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
+#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
+#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
+#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
+#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
+#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
+#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
+#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
+#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
+#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
+#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
+#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
+#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
+#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
+#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
+#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
+#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
+#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
+#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
+#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
+#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
+#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
+#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
+#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
+#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
+#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
+#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
+#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
+#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
+#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
+#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
+#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
+#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
+#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
+#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
+#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
+#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
+#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
+#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
+#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
+#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
+#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
+#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
+#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
+#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
+#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
+#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
+#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
+#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
+#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
+#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
+#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
+#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
+#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
+#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
+#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
+#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
+#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
+#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
+#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
+#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
+#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
+#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
+#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
+#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
+#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
+#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
+#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
+#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
+#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
+#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
+#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
+#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
+#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
+#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
+#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
+#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
+#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
+#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
+#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
+#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
+#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
+#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
+#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
+#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
+#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
+#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
+#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
+#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
+#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
+#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
+#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
+#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
+#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
+#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
+#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
+#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
+#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
+#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
+#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
+#define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_read_SPORT2_TX()          bfin_read32(SPORT2_TX)
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_read_SPORT3_TX()          bfin_read32(SPORT3_TX)
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
+#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
+#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
+#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
+#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
+#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
+#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
+#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
+#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
+#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
+#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
+#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
+#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
+#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
+#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
+#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
+#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
+#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
+#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
+#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
+#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF548_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h
new file mode 100644
index 0000000000..a92479bc67
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h
@@ -0,0 +1,1937 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF548_extended__
+#define __BFIN_DEF_ADSP_EDN_BF548_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
+#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
+#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
+#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
+#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
+#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
+#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
+#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
+#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
+#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
+#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
+#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
+#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
+#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
+#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
+#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
+#define UART2_LCR                      0xFFC0210C /* Line Control Register */
+#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
+#define UART2_LSR                      0xFFC02114 /* Line Status Register */
+#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
+#define UART2_SCR                      0xFFC0211C /* Scratch Register */
+#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
+#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
+#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+#define USB_FADDR                      0xFFC03C00 /* Function address register */
+#define USB_POWER                      0xFFC03C04 /* Power management register */
+#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03C20 /* USB frame number */
+#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF548_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
new file mode 100644
index 0000000000..c5d3511b0b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
@@ -0,0 +1,6139 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF549_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF549_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
+#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
+#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
+#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
+#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
+#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
+#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
+#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
+#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
+#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
+#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
+#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
+#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
+#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
+#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
+#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
+#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
+#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
+#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
+#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
+#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
+#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
+#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
+#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
+#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
+#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
+#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
+#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
+#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
+#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pMXVR_CONFIG                   ((uint16_t volatile *)MXVR_CONFIG) /* MXVR Configuration Register */
+#define bfin_read_MXVR_CONFIG()        bfin_read16(MXVR_CONFIG)
+#define bfin_write_MXVR_CONFIG(val)    bfin_write16(MXVR_CONFIG, val)
+#define pMXVR_STATE_0                  ((uint32_t volatile *)MXVR_STATE_0) /* MXVR State Register 0 */
+#define bfin_read_MXVR_STATE_0()       bfin_read32(MXVR_STATE_0)
+#define bfin_write_MXVR_STATE_0(val)   bfin_write32(MXVR_STATE_0, val)
+#define pMXVR_STATE_1                  ((uint32_t volatile *)MXVR_STATE_1) /* MXVR State Register 1 */
+#define bfin_read_MXVR_STATE_1()       bfin_read32(MXVR_STATE_1)
+#define bfin_write_MXVR_STATE_1(val)   bfin_write32(MXVR_STATE_1, val)
+#define pMXVR_INT_STAT_0               ((uint32_t volatile *)MXVR_INT_STAT_0) /* MXVR Interrupt Status Register 0 */
+#define bfin_read_MXVR_INT_STAT_0()    bfin_read32(MXVR_INT_STAT_0)
+#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
+#define pMXVR_INT_STAT_1               ((uint32_t volatile *)MXVR_INT_STAT_1) /* MXVR Interrupt Status Register 1 */
+#define bfin_read_MXVR_INT_STAT_1()    bfin_read32(MXVR_INT_STAT_1)
+#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
+#define pMXVR_INT_EN_0                 ((uint32_t volatile *)MXVR_INT_EN_0) /* MXVR Interrupt Enable Register 0 */
+#define bfin_read_MXVR_INT_EN_0()      bfin_read32(MXVR_INT_EN_0)
+#define bfin_write_MXVR_INT_EN_0(val)  bfin_write32(MXVR_INT_EN_0, val)
+#define pMXVR_INT_EN_1                 ((uint32_t volatile *)MXVR_INT_EN_1) /* MXVR Interrupt Enable Register 1 */
+#define bfin_read_MXVR_INT_EN_1()      bfin_read32(MXVR_INT_EN_1)
+#define bfin_write_MXVR_INT_EN_1(val)  bfin_write32(MXVR_INT_EN_1, val)
+#define pMXVR_POSITION                 ((uint16_t volatile *)MXVR_POSITION) /* MXVR Node Position Register */
+#define bfin_read_MXVR_POSITION()      bfin_read16(MXVR_POSITION)
+#define bfin_write_MXVR_POSITION(val)  bfin_write16(MXVR_POSITION, val)
+#define pMXVR_MAX_POSITION             ((uint16_t volatile *)MXVR_MAX_POSITION) /* MXVR Maximum Node Position Register */
+#define bfin_read_MXVR_MAX_POSITION()  bfin_read16(MXVR_MAX_POSITION)
+#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
+#define pMXVR_DELAY                    ((uint16_t volatile *)MXVR_DELAY) /* MXVR Node Frame Delay Register */
+#define bfin_read_MXVR_DELAY()         bfin_read16(MXVR_DELAY)
+#define bfin_write_MXVR_DELAY(val)     bfin_write16(MXVR_DELAY, val)
+#define pMXVR_MAX_DELAY                ((uint16_t volatile *)MXVR_MAX_DELAY) /* MXVR Maximum Node Frame Delay Register */
+#define bfin_read_MXVR_MAX_DELAY()     bfin_read16(MXVR_MAX_DELAY)
+#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
+#define pMXVR_LADDR                    ((uint32_t volatile *)MXVR_LADDR) /* MXVR Logical Address Register */
+#define bfin_read_MXVR_LADDR()         bfin_read32(MXVR_LADDR)
+#define bfin_write_MXVR_LADDR(val)     bfin_write32(MXVR_LADDR, val)
+#define pMXVR_GADDR                    ((uint16_t volatile *)MXVR_GADDR) /* MXVR Group Address Register */
+#define bfin_read_MXVR_GADDR()         bfin_read16(MXVR_GADDR)
+#define bfin_write_MXVR_GADDR(val)     bfin_write16(MXVR_GADDR, val)
+#define pMXVR_AADDR                    ((uint32_t volatile *)MXVR_AADDR) /* MXVR Alternate Address Register */
+#define bfin_read_MXVR_AADDR()         bfin_read32(MXVR_AADDR)
+#define bfin_write_MXVR_AADDR(val)     bfin_write32(MXVR_AADDR, val)
+#define pMXVR_ALLOC_0                  ((uint32_t volatile *)MXVR_ALLOC_0) /* MXVR Allocation Table Register 0 */
+#define bfin_read_MXVR_ALLOC_0()       bfin_read32(MXVR_ALLOC_0)
+#define bfin_write_MXVR_ALLOC_0(val)   bfin_write32(MXVR_ALLOC_0, val)
+#define pMXVR_ALLOC_1                  ((uint32_t volatile *)MXVR_ALLOC_1) /* MXVR Allocation Table Register 1 */
+#define bfin_read_MXVR_ALLOC_1()       bfin_read32(MXVR_ALLOC_1)
+#define bfin_write_MXVR_ALLOC_1(val)   bfin_write32(MXVR_ALLOC_1, val)
+#define pMXVR_ALLOC_2                  ((uint32_t volatile *)MXVR_ALLOC_2) /* MXVR Allocation Table Register 2 */
+#define bfin_read_MXVR_ALLOC_2()       bfin_read32(MXVR_ALLOC_2)
+#define bfin_write_MXVR_ALLOC_2(val)   bfin_write32(MXVR_ALLOC_2, val)
+#define pMXVR_ALLOC_3                  ((uint32_t volatile *)MXVR_ALLOC_3) /* MXVR Allocation Table Register 3 */
+#define bfin_read_MXVR_ALLOC_3()       bfin_read32(MXVR_ALLOC_3)
+#define bfin_write_MXVR_ALLOC_3(val)   bfin_write32(MXVR_ALLOC_3, val)
+#define pMXVR_ALLOC_4                  ((uint32_t volatile *)MXVR_ALLOC_4) /* MXVR Allocation Table Register 4 */
+#define bfin_read_MXVR_ALLOC_4()       bfin_read32(MXVR_ALLOC_4)
+#define bfin_write_MXVR_ALLOC_4(val)   bfin_write32(MXVR_ALLOC_4, val)
+#define pMXVR_ALLOC_5                  ((uint32_t volatile *)MXVR_ALLOC_5) /* MXVR Allocation Table Register 5 */
+#define bfin_read_MXVR_ALLOC_5()       bfin_read32(MXVR_ALLOC_5)
+#define bfin_write_MXVR_ALLOC_5(val)   bfin_write32(MXVR_ALLOC_5, val)
+#define pMXVR_ALLOC_6                  ((uint32_t volatile *)MXVR_ALLOC_6) /* MXVR Allocation Table Register 6 */
+#define bfin_read_MXVR_ALLOC_6()       bfin_read32(MXVR_ALLOC_6)
+#define bfin_write_MXVR_ALLOC_6(val)   bfin_write32(MXVR_ALLOC_6, val)
+#define pMXVR_ALLOC_7                  ((uint32_t volatile *)MXVR_ALLOC_7) /* MXVR Allocation Table Register 7 */
+#define bfin_read_MXVR_ALLOC_7()       bfin_read32(MXVR_ALLOC_7)
+#define bfin_write_MXVR_ALLOC_7(val)   bfin_write32(MXVR_ALLOC_7, val)
+#define pMXVR_ALLOC_8                  ((uint32_t volatile *)MXVR_ALLOC_8) /* MXVR Allocation Table Register 8 */
+#define bfin_read_MXVR_ALLOC_8()       bfin_read32(MXVR_ALLOC_8)
+#define bfin_write_MXVR_ALLOC_8(val)   bfin_write32(MXVR_ALLOC_8, val)
+#define pMXVR_ALLOC_9                  ((uint32_t volatile *)MXVR_ALLOC_9) /* MXVR Allocation Table Register 9 */
+#define bfin_read_MXVR_ALLOC_9()       bfin_read32(MXVR_ALLOC_9)
+#define bfin_write_MXVR_ALLOC_9(val)   bfin_write32(MXVR_ALLOC_9, val)
+#define pMXVR_ALLOC_10                 ((uint32_t volatile *)MXVR_ALLOC_10) /* MXVR Allocation Table Register 10 */
+#define bfin_read_MXVR_ALLOC_10()      bfin_read32(MXVR_ALLOC_10)
+#define bfin_write_MXVR_ALLOC_10(val)  bfin_write32(MXVR_ALLOC_10, val)
+#define pMXVR_ALLOC_11                 ((uint32_t volatile *)MXVR_ALLOC_11) /* MXVR Allocation Table Register 11 */
+#define bfin_read_MXVR_ALLOC_11()      bfin_read32(MXVR_ALLOC_11)
+#define bfin_write_MXVR_ALLOC_11(val)  bfin_write32(MXVR_ALLOC_11, val)
+#define pMXVR_ALLOC_12                 ((uint32_t volatile *)MXVR_ALLOC_12) /* MXVR Allocation Table Register 12 */
+#define bfin_read_MXVR_ALLOC_12()      bfin_read32(MXVR_ALLOC_12)
+#define bfin_write_MXVR_ALLOC_12(val)  bfin_write32(MXVR_ALLOC_12, val)
+#define pMXVR_ALLOC_13                 ((uint32_t volatile *)MXVR_ALLOC_13) /* MXVR Allocation Table Register 13 */
+#define bfin_read_MXVR_ALLOC_13()      bfin_read32(MXVR_ALLOC_13)
+#define bfin_write_MXVR_ALLOC_13(val)  bfin_write32(MXVR_ALLOC_13, val)
+#define pMXVR_ALLOC_14                 ((uint32_t volatile *)MXVR_ALLOC_14) /* MXVR Allocation Table Register 14 */
+#define bfin_read_MXVR_ALLOC_14()      bfin_read32(MXVR_ALLOC_14)
+#define bfin_write_MXVR_ALLOC_14(val)  bfin_write32(MXVR_ALLOC_14, val)
+#define pMXVR_SYNC_LCHAN_0             ((uint32_t volatile *)MXVR_SYNC_LCHAN_0) /* MXVR Sync Data Logical Channel Assign Register 0 */
+#define bfin_read_MXVR_SYNC_LCHAN_0()  bfin_read32(MXVR_SYNC_LCHAN_0)
+#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
+#define pMXVR_SYNC_LCHAN_1             ((uint32_t volatile *)MXVR_SYNC_LCHAN_1) /* MXVR Sync Data Logical Channel Assign Register 1 */
+#define bfin_read_MXVR_SYNC_LCHAN_1()  bfin_read32(MXVR_SYNC_LCHAN_1)
+#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
+#define pMXVR_SYNC_LCHAN_2             ((uint32_t volatile *)MXVR_SYNC_LCHAN_2) /* MXVR Sync Data Logical Channel Assign Register 2 */
+#define bfin_read_MXVR_SYNC_LCHAN_2()  bfin_read32(MXVR_SYNC_LCHAN_2)
+#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
+#define pMXVR_SYNC_LCHAN_3             ((uint32_t volatile *)MXVR_SYNC_LCHAN_3) /* MXVR Sync Data Logical Channel Assign Register 3 */
+#define bfin_read_MXVR_SYNC_LCHAN_3()  bfin_read32(MXVR_SYNC_LCHAN_3)
+#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
+#define pMXVR_SYNC_LCHAN_4             ((uint32_t volatile *)MXVR_SYNC_LCHAN_4) /* MXVR Sync Data Logical Channel Assign Register 4 */
+#define bfin_read_MXVR_SYNC_LCHAN_4()  bfin_read32(MXVR_SYNC_LCHAN_4)
+#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
+#define pMXVR_SYNC_LCHAN_5             ((uint32_t volatile *)MXVR_SYNC_LCHAN_5) /* MXVR Sync Data Logical Channel Assign Register 5 */
+#define bfin_read_MXVR_SYNC_LCHAN_5()  bfin_read32(MXVR_SYNC_LCHAN_5)
+#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
+#define pMXVR_SYNC_LCHAN_6             ((uint32_t volatile *)MXVR_SYNC_LCHAN_6) /* MXVR Sync Data Logical Channel Assign Register 6 */
+#define bfin_read_MXVR_SYNC_LCHAN_6()  bfin_read32(MXVR_SYNC_LCHAN_6)
+#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
+#define pMXVR_SYNC_LCHAN_7             ((uint32_t volatile *)MXVR_SYNC_LCHAN_7) /* MXVR Sync Data Logical Channel Assign Register 7 */
+#define bfin_read_MXVR_SYNC_LCHAN_7()  bfin_read32(MXVR_SYNC_LCHAN_7)
+#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
+#define pMXVR_DMA0_CONFIG              ((uint32_t volatile *)MXVR_DMA0_CONFIG) /* MXVR Sync Data DMA0 Config Register */
+#define bfin_read_MXVR_DMA0_CONFIG()   bfin_read32(MXVR_DMA0_CONFIG)
+#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
+#define pMXVR_DMA0_START_ADDR          ((void * volatile *)MXVR_DMA0_START_ADDR) /* MXVR Sync Data DMA0 Start Address */
+#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
+#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
+#define pMXVR_DMA0_COUNT               ((uint16_t volatile *)MXVR_DMA0_COUNT) /* MXVR Sync Data DMA0 Loop Count Register */
+#define bfin_read_MXVR_DMA0_COUNT()    bfin_read16(MXVR_DMA0_COUNT)
+#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
+#define pMXVR_DMA0_CURR_ADDR           ((void * volatile *)MXVR_DMA0_CURR_ADDR) /* MXVR Sync Data DMA0 Current Address */
+#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
+#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
+#define pMXVR_DMA0_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA0_CURR_COUNT) /* MXVR Sync Data DMA0 Current Loop Count */
+#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
+#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
+#define pMXVR_DMA1_CONFIG              ((uint32_t volatile *)MXVR_DMA1_CONFIG) /* MXVR Sync Data DMA1 Config Register */
+#define bfin_read_MXVR_DMA1_CONFIG()   bfin_read32(MXVR_DMA1_CONFIG)
+#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
+#define pMXVR_DMA1_START_ADDR          ((void * volatile *)MXVR_DMA1_START_ADDR) /* MXVR Sync Data DMA1 Start Address */
+#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
+#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
+#define pMXVR_DMA1_COUNT               ((uint16_t volatile *)MXVR_DMA1_COUNT) /* MXVR Sync Data DMA1 Loop Count Register */
+#define bfin_read_MXVR_DMA1_COUNT()    bfin_read16(MXVR_DMA1_COUNT)
+#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
+#define pMXVR_DMA1_CURR_ADDR           ((void * volatile *)MXVR_DMA1_CURR_ADDR) /* MXVR Sync Data DMA1 Current Address */
+#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
+#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
+#define pMXVR_DMA1_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA1_CURR_COUNT) /* MXVR Sync Data DMA1 Current Loop Count */
+#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
+#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
+#define pMXVR_DMA2_CONFIG              ((uint32_t volatile *)MXVR_DMA2_CONFIG) /* MXVR Sync Data DMA2 Config Register */
+#define bfin_read_MXVR_DMA2_CONFIG()   bfin_read32(MXVR_DMA2_CONFIG)
+#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
+#define pMXVR_DMA2_START_ADDR          ((void * volatile *)MXVR_DMA2_START_ADDR) /* MXVR Sync Data DMA2 Start Address */
+#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
+#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
+#define pMXVR_DMA2_COUNT               ((uint16_t volatile *)MXVR_DMA2_COUNT) /* MXVR Sync Data DMA2 Loop Count Register */
+#define bfin_read_MXVR_DMA2_COUNT()    bfin_read16(MXVR_DMA2_COUNT)
+#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
+#define pMXVR_DMA2_CURR_ADDR           ((void * volatile *)MXVR_DMA2_CURR_ADDR) /* MXVR Sync Data DMA2 Current Address */
+#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
+#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
+#define pMXVR_DMA2_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA2_CURR_COUNT) /* MXVR Sync Data DMA2 Current Loop Count */
+#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
+#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
+#define pMXVR_DMA3_CONFIG              ((uint32_t volatile *)MXVR_DMA3_CONFIG) /* MXVR Sync Data DMA3 Config Register */
+#define bfin_read_MXVR_DMA3_CONFIG()   bfin_read32(MXVR_DMA3_CONFIG)
+#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
+#define pMXVR_DMA3_START_ADDR          ((void * volatile *)MXVR_DMA3_START_ADDR) /* MXVR Sync Data DMA3 Start Address */
+#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
+#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
+#define pMXVR_DMA3_COUNT               ((uint16_t volatile *)MXVR_DMA3_COUNT) /* MXVR Sync Data DMA3 Loop Count Register */
+#define bfin_read_MXVR_DMA3_COUNT()    bfin_read16(MXVR_DMA3_COUNT)
+#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
+#define pMXVR_DMA3_CURR_ADDR           ((void * volatile *)MXVR_DMA3_CURR_ADDR) /* MXVR Sync Data DMA3 Current Address */
+#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
+#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
+#define pMXVR_DMA3_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA3_CURR_COUNT) /* MXVR Sync Data DMA3 Current Loop Count */
+#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
+#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
+#define pMXVR_DMA4_CONFIG              ((uint32_t volatile *)MXVR_DMA4_CONFIG) /* MXVR Sync Data DMA4 Config Register */
+#define bfin_read_MXVR_DMA4_CONFIG()   bfin_read32(MXVR_DMA4_CONFIG)
+#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
+#define pMXVR_DMA4_START_ADDR          ((void * volatile *)MXVR_DMA4_START_ADDR) /* MXVR Sync Data DMA4 Start Address */
+#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
+#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
+#define pMXVR_DMA4_COUNT               ((uint16_t volatile *)MXVR_DMA4_COUNT) /* MXVR Sync Data DMA4 Loop Count Register */
+#define bfin_read_MXVR_DMA4_COUNT()    bfin_read16(MXVR_DMA4_COUNT)
+#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
+#define pMXVR_DMA4_CURR_ADDR           ((void * volatile *)MXVR_DMA4_CURR_ADDR) /* MXVR Sync Data DMA4 Current Address */
+#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
+#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
+#define pMXVR_DMA4_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA4_CURR_COUNT) /* MXVR Sync Data DMA4 Current Loop Count */
+#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
+#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
+#define pMXVR_DMA5_CONFIG              ((uint32_t volatile *)MXVR_DMA5_CONFIG) /* MXVR Sync Data DMA5 Config Register */
+#define bfin_read_MXVR_DMA5_CONFIG()   bfin_read32(MXVR_DMA5_CONFIG)
+#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
+#define pMXVR_DMA5_START_ADDR          ((void * volatile *)MXVR_DMA5_START_ADDR) /* MXVR Sync Data DMA5 Start Address */
+#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
+#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
+#define pMXVR_DMA5_COUNT               ((uint16_t volatile *)MXVR_DMA5_COUNT) /* MXVR Sync Data DMA5 Loop Count Register */
+#define bfin_read_MXVR_DMA5_COUNT()    bfin_read16(MXVR_DMA5_COUNT)
+#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
+#define pMXVR_DMA5_CURR_ADDR           ((void * volatile *)MXVR_DMA5_CURR_ADDR) /* MXVR Sync Data DMA5 Current Address */
+#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
+#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
+#define pMXVR_DMA5_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA5_CURR_COUNT) /* MXVR Sync Data DMA5 Current Loop Count */
+#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
+#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
+#define pMXVR_DMA6_CONFIG              ((uint32_t volatile *)MXVR_DMA6_CONFIG) /* MXVR Sync Data DMA6 Config Register */
+#define bfin_read_MXVR_DMA6_CONFIG()   bfin_read32(MXVR_DMA6_CONFIG)
+#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
+#define pMXVR_DMA6_START_ADDR          ((void * volatile *)MXVR_DMA6_START_ADDR) /* MXVR Sync Data DMA6 Start Address */
+#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
+#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
+#define pMXVR_DMA6_COUNT               ((uint16_t volatile *)MXVR_DMA6_COUNT) /* MXVR Sync Data DMA6 Loop Count Register */
+#define bfin_read_MXVR_DMA6_COUNT()    bfin_read16(MXVR_DMA6_COUNT)
+#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
+#define pMXVR_DMA6_CURR_ADDR           ((void * volatile *)MXVR_DMA6_CURR_ADDR) /* MXVR Sync Data DMA6 Current Address */
+#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
+#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
+#define pMXVR_DMA6_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA6_CURR_COUNT) /* MXVR Sync Data DMA6 Current Loop Count */
+#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
+#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
+#define pMXVR_DMA7_CONFIG              ((uint32_t volatile *)MXVR_DMA7_CONFIG) /* MXVR Sync Data DMA7 Config Register */
+#define bfin_read_MXVR_DMA7_CONFIG()   bfin_read32(MXVR_DMA7_CONFIG)
+#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
+#define pMXVR_DMA7_START_ADDR          ((void * volatile *)MXVR_DMA7_START_ADDR) /* MXVR Sync Data DMA7 Start Address */
+#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
+#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
+#define pMXVR_DMA7_COUNT               ((uint16_t volatile *)MXVR_DMA7_COUNT) /* MXVR Sync Data DMA7 Loop Count Register */
+#define bfin_read_MXVR_DMA7_COUNT()    bfin_read16(MXVR_DMA7_COUNT)
+#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
+#define pMXVR_DMA7_CURR_ADDR           ((void * volatile *)MXVR_DMA7_CURR_ADDR) /* MXVR Sync Data DMA7 Current Address */
+#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
+#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
+#define pMXVR_DMA7_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA7_CURR_COUNT) /* MXVR Sync Data DMA7 Current Loop Count */
+#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
+#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
+#define pMXVR_AP_CTL                   ((uint16_t volatile *)MXVR_AP_CTL) /* MXVR Async Packet Control Register */
+#define bfin_read_MXVR_AP_CTL()        bfin_read16(MXVR_AP_CTL)
+#define bfin_write_MXVR_AP_CTL(val)    bfin_write16(MXVR_AP_CTL, val)
+#define pMXVR_APRB_START_ADDR          ((void * volatile *)MXVR_APRB_START_ADDR) /* MXVR Async Packet RX Buffer Start Addr Register */
+#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
+#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
+#define pMXVR_APRB_CURR_ADDR           ((void * volatile *)MXVR_APRB_CURR_ADDR) /* MXVR Async Packet RX Buffer Current Addr Register */
+#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
+#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
+#define pMXVR_APTB_START_ADDR          ((void * volatile *)MXVR_APTB_START_ADDR) /* MXVR Async Packet TX Buffer Start Addr Register */
+#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
+#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
+#define pMXVR_APTB_CURR_ADDR           ((void * volatile *)MXVR_APTB_CURR_ADDR) /* MXVR Async Packet TX Buffer Current Addr Register */
+#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
+#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
+#define pMXVR_CM_CTL                   ((uint32_t volatile *)MXVR_CM_CTL) /* MXVR Control Message Control Register */
+#define bfin_read_MXVR_CM_CTL()        bfin_read32(MXVR_CM_CTL)
+#define bfin_write_MXVR_CM_CTL(val)    bfin_write32(MXVR_CM_CTL, val)
+#define pMXVR_CMRB_START_ADDR          ((void * volatile *)MXVR_CMRB_START_ADDR) /* MXVR Control Message RX Buffer Start Addr Register */
+#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
+#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
+#define pMXVR_CMRB_CURR_ADDR           ((void * volatile *)MXVR_CMRB_CURR_ADDR) /* MXVR Control Message RX Buffer Current Address */
+#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
+#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
+#define pMXVR_CMTB_START_ADDR          ((void * volatile *)MXVR_CMTB_START_ADDR) /* MXVR Control Message TX Buffer Start Addr Register */
+#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
+#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
+#define pMXVR_CMTB_CURR_ADDR           ((void * volatile *)MXVR_CMTB_CURR_ADDR) /* MXVR Control Message TX Buffer Current Address */
+#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
+#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
+#define pMXVR_RRDB_START_ADDR          ((void * volatile *)MXVR_RRDB_START_ADDR) /* MXVR Remote Read Buffer Start Addr Register */
+#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
+#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
+#define pMXVR_RRDB_CURR_ADDR           ((void * volatile *)MXVR_RRDB_CURR_ADDR) /* MXVR Remote Read Buffer Current Addr Register */
+#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
+#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
+#define pMXVR_PAT_DATA_0               ((uint32_t volatile *)MXVR_PAT_DATA_0) /* MXVR Pattern Data Register 0 */
+#define bfin_read_MXVR_PAT_DATA_0()    bfin_read32(MXVR_PAT_DATA_0)
+#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
+#define pMXVR_PAT_EN_0                 ((uint32_t volatile *)MXVR_PAT_EN_0) /* MXVR Pattern Enable Register 0 */
+#define bfin_read_MXVR_PAT_EN_0()      bfin_read32(MXVR_PAT_EN_0)
+#define bfin_write_MXVR_PAT_EN_0(val)  bfin_write32(MXVR_PAT_EN_0, val)
+#define pMXVR_PAT_DATA_1               ((uint32_t volatile *)MXVR_PAT_DATA_1) /* MXVR Pattern Data Register 1 */
+#define bfin_read_MXVR_PAT_DATA_1()    bfin_read32(MXVR_PAT_DATA_1)
+#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
+#define pMXVR_PAT_EN_1                 ((uint32_t volatile *)MXVR_PAT_EN_1) /* MXVR Pattern Enable Register 1 */
+#define bfin_read_MXVR_PAT_EN_1()      bfin_read32(MXVR_PAT_EN_1)
+#define bfin_write_MXVR_PAT_EN_1(val)  bfin_write32(MXVR_PAT_EN_1, val)
+#define pMXVR_FRAME_CNT_0              ((uint16_t volatile *)MXVR_FRAME_CNT_0) /* MXVR Frame Counter 0 */
+#define bfin_read_MXVR_FRAME_CNT_0()   bfin_read16(MXVR_FRAME_CNT_0)
+#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
+#define pMXVR_FRAME_CNT_1              ((uint16_t volatile *)MXVR_FRAME_CNT_1) /* MXVR Frame Counter 1 */
+#define bfin_read_MXVR_FRAME_CNT_1()   bfin_read16(MXVR_FRAME_CNT_1)
+#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
+#define pMXVR_ROUTING_0                ((uint32_t volatile *)MXVR_ROUTING_0) /* MXVR Routing Table Register 0 */
+#define bfin_read_MXVR_ROUTING_0()     bfin_read32(MXVR_ROUTING_0)
+#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
+#define pMXVR_ROUTING_1                ((uint32_t volatile *)MXVR_ROUTING_1) /* MXVR Routing Table Register 1 */
+#define bfin_read_MXVR_ROUTING_1()     bfin_read32(MXVR_ROUTING_1)
+#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
+#define pMXVR_ROUTING_2                ((uint32_t volatile *)MXVR_ROUTING_2) /* MXVR Routing Table Register 2 */
+#define bfin_read_MXVR_ROUTING_2()     bfin_read32(MXVR_ROUTING_2)
+#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
+#define pMXVR_ROUTING_3                ((uint32_t volatile *)MXVR_ROUTING_3) /* MXVR Routing Table Register 3 */
+#define bfin_read_MXVR_ROUTING_3()     bfin_read32(MXVR_ROUTING_3)
+#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
+#define pMXVR_ROUTING_4                ((uint32_t volatile *)MXVR_ROUTING_4) /* MXVR Routing Table Register 4 */
+#define bfin_read_MXVR_ROUTING_4()     bfin_read32(MXVR_ROUTING_4)
+#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
+#define pMXVR_ROUTING_5                ((uint32_t volatile *)MXVR_ROUTING_5) /* MXVR Routing Table Register 5 */
+#define bfin_read_MXVR_ROUTING_5()     bfin_read32(MXVR_ROUTING_5)
+#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
+#define pMXVR_ROUTING_6                ((uint32_t volatile *)MXVR_ROUTING_6) /* MXVR Routing Table Register 6 */
+#define bfin_read_MXVR_ROUTING_6()     bfin_read32(MXVR_ROUTING_6)
+#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
+#define pMXVR_ROUTING_7                ((uint32_t volatile *)MXVR_ROUTING_7) /* MXVR Routing Table Register 7 */
+#define bfin_read_MXVR_ROUTING_7()     bfin_read32(MXVR_ROUTING_7)
+#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
+#define pMXVR_ROUTING_8                ((uint32_t volatile *)MXVR_ROUTING_8) /* MXVR Routing Table Register 8 */
+#define bfin_read_MXVR_ROUTING_8()     bfin_read32(MXVR_ROUTING_8)
+#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
+#define pMXVR_ROUTING_9                ((uint32_t volatile *)MXVR_ROUTING_9) /* MXVR Routing Table Register 9 */
+#define bfin_read_MXVR_ROUTING_9()     bfin_read32(MXVR_ROUTING_9)
+#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
+#define pMXVR_ROUTING_10               ((uint32_t volatile *)MXVR_ROUTING_10) /* MXVR Routing Table Register 10 */
+#define bfin_read_MXVR_ROUTING_10()    bfin_read32(MXVR_ROUTING_10)
+#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
+#define pMXVR_ROUTING_11               ((uint32_t volatile *)MXVR_ROUTING_11) /* MXVR Routing Table Register 11 */
+#define bfin_read_MXVR_ROUTING_11()    bfin_read32(MXVR_ROUTING_11)
+#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
+#define pMXVR_ROUTING_12               ((uint32_t volatile *)MXVR_ROUTING_12) /* MXVR Routing Table Register 12 */
+#define bfin_read_MXVR_ROUTING_12()    bfin_read32(MXVR_ROUTING_12)
+#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
+#define pMXVR_ROUTING_13               ((uint32_t volatile *)MXVR_ROUTING_13) /* MXVR Routing Table Register 13 */
+#define bfin_read_MXVR_ROUTING_13()    bfin_read32(MXVR_ROUTING_13)
+#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
+#define pMXVR_ROUTING_14               ((uint32_t volatile *)MXVR_ROUTING_14) /* MXVR Routing Table Register 14 */
+#define bfin_read_MXVR_ROUTING_14()    bfin_read32(MXVR_ROUTING_14)
+#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
+#define pMXVR_BLOCK_CNT                ((uint16_t volatile *)MXVR_BLOCK_CNT) /* MXVR Block Counter */
+#define bfin_read_MXVR_BLOCK_CNT()     bfin_read16(MXVR_BLOCK_CNT)
+#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
+#define pMXVR_CLK_CTL                  ((uint32_t volatile *)MXVR_CLK_CTL) /* MXVR Clock Control Register */
+#define bfin_read_MXVR_CLK_CTL()       bfin_read32(MXVR_CLK_CTL)
+#define bfin_write_MXVR_CLK_CTL(val)   bfin_write32(MXVR_CLK_CTL, val)
+#define pMXVR_CDRPLL_CTL               ((uint32_t volatile *)MXVR_CDRPLL_CTL) /* MXVR Clock/Data Recovery PLL Control Register */
+#define bfin_read_MXVR_CDRPLL_CTL()    bfin_read32(MXVR_CDRPLL_CTL)
+#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
+#define pMXVR_FMPLL_CTL                ((uint32_t volatile *)MXVR_FMPLL_CTL) /* MXVR Frequency Multiply PLL Control Register */
+#define bfin_read_MXVR_FMPLL_CTL()     bfin_read32(MXVR_FMPLL_CTL)
+#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
+#define pMXVR_PIN_CTL                  ((uint16_t volatile *)MXVR_PIN_CTL) /* MXVR Pin Control Register */
+#define bfin_read_MXVR_PIN_CTL()       bfin_read16(MXVR_PIN_CTL)
+#define bfin_write_MXVR_PIN_CTL(val)   bfin_write16(MXVR_PIN_CTL, val)
+#define pMXVR_SCLK_CNT                 ((uint16_t volatile *)MXVR_SCLK_CNT) /* MXVR System Clock Counter Register */
+#define bfin_read_MXVR_SCLK_CNT()      bfin_read16(MXVR_SCLK_CNT)
+#define bfin_write_MXVR_SCLK_CNT(val)  bfin_write16(MXVR_SCLK_CNT, val)
+#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
+#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
+#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
+#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
+#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
+#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
+#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
+#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
+#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
+#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
+#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
+#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
+#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
+#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
+#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
+#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
+#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
+#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
+#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
+#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
+#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
+#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
+#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
+#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
+#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
+#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
+#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
+#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
+#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
+#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
+#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
+#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
+#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
+#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
+#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
+#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
+#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
+#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
+#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
+#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
+#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
+#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
+#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
+#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
+#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
+#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
+#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
+#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
+#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
+#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
+#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
+#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
+#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
+#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
+#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
+#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
+#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
+#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
+#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
+#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
+#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
+#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
+#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
+#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
+#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
+#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
+#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
+#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
+#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
+#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
+#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
+#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
+#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
+#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
+#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
+#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
+#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
+#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
+#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
+#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
+#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
+#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
+#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
+#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
+#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
+#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
+#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
+#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
+#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
+#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
+#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
+#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
+#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
+#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
+#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
+#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
+#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
+#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
+#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
+#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
+#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
+#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
+#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
+#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
+#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
+#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
+#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
+#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
+#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
+#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
+#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
+#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
+#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
+#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
+#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
+#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
+#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
+#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
+#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
+#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
+#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
+#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
+#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
+#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
+#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
+#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
+#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
+#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
+#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
+#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
+#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
+#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
+#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
+#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
+#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
+#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
+#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
+#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
+#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
+#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
+#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
+#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
+#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
+#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
+#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
+#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
+#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
+#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
+#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
+#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
+#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
+#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
+#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
+#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
+#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
+#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
+#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
+#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
+#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
+#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
+#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
+#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
+#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
+#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
+#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
+#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
+#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
+#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
+#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
+#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
+#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
+#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
+#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
+#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
+#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
+#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
+#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
+#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
+#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
+#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
+#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
+#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
+#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
+#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
+#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
+#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
+#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
+#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
+#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
+#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
+#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
+#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
+#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
+#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
+#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
+#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
+#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
+#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
+#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
+#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
+#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
+#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
+#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
+#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
+#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
+#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
+#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
+#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
+#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
+#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
+#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
+#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
+#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
+#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
+#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
+#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
+#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
+#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
+#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
+#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
+#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
+#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
+#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
+#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
+#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
+#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
+#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
+#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
+#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
+#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
+#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
+#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
+#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
+#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
+#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
+#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
+#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
+#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
+#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
+#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
+#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
+#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
+#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
+#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
+#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
+#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
+#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
+#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
+#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
+#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
+#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
+#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
+#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
+#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
+#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
+#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
+#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
+#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
+#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
+#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
+#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
+#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
+#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
+#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
+#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
+#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
+#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
+#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
+#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
+#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
+#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
+#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
+#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
+#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
+#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
+#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
+#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
+#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
+#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
+#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
+#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
+#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
+#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
+#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
+#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
+#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
+#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
+#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
+#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
+#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
+#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
+#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
+#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
+#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
+#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
+#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
+#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
+#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
+#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
+#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
+#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
+#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
+#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
+#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
+#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
+#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
+#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
+#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
+#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
+#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
+#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
+#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
+#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
+#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
+#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
+#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
+#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
+#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
+#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
+#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
+#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
+#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
+#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
+#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
+#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
+#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
+#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
+#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
+#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
+#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
+#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
+#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
+#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
+#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
+#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
+#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
+#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
+#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
+#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
+#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
+#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
+#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
+#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
+#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
+#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
+#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
+#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
+#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
+#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
+#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
+#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
+#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
+#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
+#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
+#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
+#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
+#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
+#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
+#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
+#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
+#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
+#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
+#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
+#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
+#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
+#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
+#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
+#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
+#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
+#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
+#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
+#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
+#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
+#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
+#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
+#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
+#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
+#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
+#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
+#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
+#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
+#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
+#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
+#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
+#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
+#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
+#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
+#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
+#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
+#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
+#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
+#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
+#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
+#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
+#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
+#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
+#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
+#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
+#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
+#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
+#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
+#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
+#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
+#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
+#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
+#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
+#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
+#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
+#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
+#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
+#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
+#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
+#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
+#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
+#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
+#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
+#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
+#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
+#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
+#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
+#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
+#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
+#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
+#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
+#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
+#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
+#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
+#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
+#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
+#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
+#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
+#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
+#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
+#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
+#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
+#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
+#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
+#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
+#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
+#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
+#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
+#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
+#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
+#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
+#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
+#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
+#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
+#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
+#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
+#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
+#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
+#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
+#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
+#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
+#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
+#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
+#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
+#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
+#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
+#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
+#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
+#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
+#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
+#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
+#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
+#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
+#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
+#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
+#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
+#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
+#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
+#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
+#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
+#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
+#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
+#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
+#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
+#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
+#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
+#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
+#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
+#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
+#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
+#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
+#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
+#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
+#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
+#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
+#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
+#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
+#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
+#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
+#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
+#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
+#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
+#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
+#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
+#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
+#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
+#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
+#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
+#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
+#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
+#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
+#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
+#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
+#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
+#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
+#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
+#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
+#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
+#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
+#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
+#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
+#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
+#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
+#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
+#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
+#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
+#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
+#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
+#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
+#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
+#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
+#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
+#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
+#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
+#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
+#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
+#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
+#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
+#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
+#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
+#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
+#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
+#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
+#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
+#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
+#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
+#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
+#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
+#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
+#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
+#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
+#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
+#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
+#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
+#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
+#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
+#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
+#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
+#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
+#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
+#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
+#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
+#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
+#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
+#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
+#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
+#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
+#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
+#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
+#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
+#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
+#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
+#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
+#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
+#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
+#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
+#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
+#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
+#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
+#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
+#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
+#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
+#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
+#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
+#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
+#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
+#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
+#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
+#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
+#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
+#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
+#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
+#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
+#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
+#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
+#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
+#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
+#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
+#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
+#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
+#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
+#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
+#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
+#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
+#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
+#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
+#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
+#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
+#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
+#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
+#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
+#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
+#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
+#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
+#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
+#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
+#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
+#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
+#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
+#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
+#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
+#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
+#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
+#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
+#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
+#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
+#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
+#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
+#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
+#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
+#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
+#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
+#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
+#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
+#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
+#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
+#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
+#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
+#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
+#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
+#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
+#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
+#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
+#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
+#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
+#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
+#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
+#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
+#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
+#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
+#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
+#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
+#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
+#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
+#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
+#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
+#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
+#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
+#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
+#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
+#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
+#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
+#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
+#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
+#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
+#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
+#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
+#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
+#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
+#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
+#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
+#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
+#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
+#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
+#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
+#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
+#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
+#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
+#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
+#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
+#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
+#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
+#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
+#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
+#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
+#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
+#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
+#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
+#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
+#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
+#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
+#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
+#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
+#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
+#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
+#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
+#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
+#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
+#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
+#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
+#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
+#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
+#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
+#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
+#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
+#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
+#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
+#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
+#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
+#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
+#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
+#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
+#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
+#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
+#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
+#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
+#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
+#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
+#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
+#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
+#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
+#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
+#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
+#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
+#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
+#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
+#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
+#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
+#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
+#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
+#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
+#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
+#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
+#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
+#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
+#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
+#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
+#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
+#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
+#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
+#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
+#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
+#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
+#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
+#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
+#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
+#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
+#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
+#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
+#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
+#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
+#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
+#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
+#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
+#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
+#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
+#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
+#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
+#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
+#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
+#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
+#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
+#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
+#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
+#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
+#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
+#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
+#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
+#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
+#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
+#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
+#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
+#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
+#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
+#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
+#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
+#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
+#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
+#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
+#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
+#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
+#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
+#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
+#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
+#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
+#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
+#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
+#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
+#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
+#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
+#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
+#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
+#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
+#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
+#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
+#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
+#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
+#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
+#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
+#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
+#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
+#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
+#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
+#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
+#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
+#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
+#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
+#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
+#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
+#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
+#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
+#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
+#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
+#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
+#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
+#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
+#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
+#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
+#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
+#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
+#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
+#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
+#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
+#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
+#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
+#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
+#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
+#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
+#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
+#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
+#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
+#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
+#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
+#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
+#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
+#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
+#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
+#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
+#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
+#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
+#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
+#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
+#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
+#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
+#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
+#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
+#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
+#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
+#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
+#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
+#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
+#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
+#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
+#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
+#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
+#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
+#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
+#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
+#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
+#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
+#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
+#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
+#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
+#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
+#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
+#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
+#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
+#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
+#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
+#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
+#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
+#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
+#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
+#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
+#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
+#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
+#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
+#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
+#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
+#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
+#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
+#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
+#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
+#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
+#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
+#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
+#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
+#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
+#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
+#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
+#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
+#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
+#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
+#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
+#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
+#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
+#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
+#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
+#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
+#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
+#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
+#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
+#define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_read_SPORT2_TX()          bfin_read32(SPORT2_TX)
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_read_SPORT3_TX()          bfin_read32(SPORT3_TX)
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
+#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
+#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
+#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
+#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
+#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
+#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
+#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
+#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
+#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
+#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
+#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
+#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
+#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
+#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
+#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
+#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
+#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
+#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
+#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
+#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF549_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_def.h
new file mode 100644
index 0000000000..6163eb276f
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_def.h
@@ -0,0 +1,2053 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF549_extended__
+#define __BFIN_DEF_ADSP_EDN_BF549_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
+#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
+#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
+#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
+#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
+#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
+#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define MXVR_CONFIG                    0xFFC02700 /* MXVR Configuration Register */
+#define MXVR_STATE_0                   0xFFC02708 /* MXVR State Register 0 */
+#define MXVR_STATE_1                   0xFFC0270C /* MXVR State Register 1 */
+#define MXVR_INT_STAT_0                0xFFC02710 /* MXVR Interrupt Status Register 0 */
+#define MXVR_INT_STAT_1                0xFFC02714 /* MXVR Interrupt Status Register 1 */
+#define MXVR_INT_EN_0                  0xFFC02718 /* MXVR Interrupt Enable Register 0 */
+#define MXVR_INT_EN_1                  0xFFC0271C /* MXVR Interrupt Enable Register 1 */
+#define MXVR_POSITION                  0xFFC02720 /* MXVR Node Position Register */
+#define MXVR_MAX_POSITION              0xFFC02724 /* MXVR Maximum Node Position Register */
+#define MXVR_DELAY                     0xFFC02728 /* MXVR Node Frame Delay Register */
+#define MXVR_MAX_DELAY                 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
+#define MXVR_LADDR                     0xFFC02730 /* MXVR Logical Address Register */
+#define MXVR_GADDR                     0xFFC02734 /* MXVR Group Address Register */
+#define MXVR_AADDR                     0xFFC02738 /* MXVR Alternate Address Register */
+#define MXVR_ALLOC_0                   0xFFC0273C /* MXVR Allocation Table Register 0 */
+#define MXVR_ALLOC_1                   0xFFC02740 /* MXVR Allocation Table Register 1 */
+#define MXVR_ALLOC_2                   0xFFC02744 /* MXVR Allocation Table Register 2 */
+#define MXVR_ALLOC_3                   0xFFC02748 /* MXVR Allocation Table Register 3 */
+#define MXVR_ALLOC_4                   0xFFC0274C /* MXVR Allocation Table Register 4 */
+#define MXVR_ALLOC_5                   0xFFC02750 /* MXVR Allocation Table Register 5 */
+#define MXVR_ALLOC_6                   0xFFC02754 /* MXVR Allocation Table Register 6 */
+#define MXVR_ALLOC_7                   0xFFC02758 /* MXVR Allocation Table Register 7 */
+#define MXVR_ALLOC_8                   0xFFC0275C /* MXVR Allocation Table Register 8 */
+#define MXVR_ALLOC_9                   0xFFC02760 /* MXVR Allocation Table Register 9 */
+#define MXVR_ALLOC_10                  0xFFC02764 /* MXVR Allocation Table Register 10 */
+#define MXVR_ALLOC_11                  0xFFC02768 /* MXVR Allocation Table Register 11 */
+#define MXVR_ALLOC_12                  0xFFC0276C /* MXVR Allocation Table Register 12 */
+#define MXVR_ALLOC_13                  0xFFC02770 /* MXVR Allocation Table Register 13 */
+#define MXVR_ALLOC_14                  0xFFC02774 /* MXVR Allocation Table Register 14 */
+#define MXVR_SYNC_LCHAN_0              0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
+#define MXVR_SYNC_LCHAN_1              0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
+#define MXVR_SYNC_LCHAN_2              0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
+#define MXVR_SYNC_LCHAN_3              0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
+#define MXVR_SYNC_LCHAN_4              0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
+#define MXVR_SYNC_LCHAN_5              0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
+#define MXVR_SYNC_LCHAN_6              0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
+#define MXVR_SYNC_LCHAN_7              0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
+#define MXVR_DMA0_CONFIG               0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
+#define MXVR_DMA0_START_ADDR           0xFFC0279C /* MXVR Sync Data DMA0 Start Address */
+#define MXVR_DMA0_COUNT                0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
+#define MXVR_DMA0_CURR_ADDR            0xFFC027A4 /* MXVR Sync Data DMA0 Current Address */
+#define MXVR_DMA0_CURR_COUNT           0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count */
+#define MXVR_DMA1_CONFIG               0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
+#define MXVR_DMA1_START_ADDR           0xFFC027B0 /* MXVR Sync Data DMA1 Start Address */
+#define MXVR_DMA1_COUNT                0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
+#define MXVR_DMA1_CURR_ADDR            0xFFC027B8 /* MXVR Sync Data DMA1 Current Address */
+#define MXVR_DMA1_CURR_COUNT           0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count */
+#define MXVR_DMA2_CONFIG               0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
+#define MXVR_DMA2_START_ADDR           0xFFC027C4 /* MXVR Sync Data DMA2 Start Address */
+#define MXVR_DMA2_COUNT                0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
+#define MXVR_DMA2_CURR_ADDR            0xFFC027CC /* MXVR Sync Data DMA2 Current Address */
+#define MXVR_DMA2_CURR_COUNT           0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count */
+#define MXVR_DMA3_CONFIG               0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
+#define MXVR_DMA3_START_ADDR           0xFFC027D8 /* MXVR Sync Data DMA3 Start Address */
+#define MXVR_DMA3_COUNT                0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
+#define MXVR_DMA3_CURR_ADDR            0xFFC027E0 /* MXVR Sync Data DMA3 Current Address */
+#define MXVR_DMA3_CURR_COUNT           0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count */
+#define MXVR_DMA4_CONFIG               0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
+#define MXVR_DMA4_START_ADDR           0xFFC027EC /* MXVR Sync Data DMA4 Start Address */
+#define MXVR_DMA4_COUNT                0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
+#define MXVR_DMA4_CURR_ADDR            0xFFC027F4 /* MXVR Sync Data DMA4 Current Address */
+#define MXVR_DMA4_CURR_COUNT           0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count */
+#define MXVR_DMA5_CONFIG               0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
+#define MXVR_DMA5_START_ADDR           0xFFC02800 /* MXVR Sync Data DMA5 Start Address */
+#define MXVR_DMA5_COUNT                0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
+#define MXVR_DMA5_CURR_ADDR            0xFFC02808 /* MXVR Sync Data DMA5 Current Address */
+#define MXVR_DMA5_CURR_COUNT           0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count */
+#define MXVR_DMA6_CONFIG               0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
+#define MXVR_DMA6_START_ADDR           0xFFC02814 /* MXVR Sync Data DMA6 Start Address */
+#define MXVR_DMA6_COUNT                0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
+#define MXVR_DMA6_CURR_ADDR            0xFFC0281C /* MXVR Sync Data DMA6 Current Address */
+#define MXVR_DMA6_CURR_COUNT           0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count */
+#define MXVR_DMA7_CONFIG               0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
+#define MXVR_DMA7_START_ADDR           0xFFC02828 /* MXVR Sync Data DMA7 Start Address */
+#define MXVR_DMA7_COUNT                0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
+#define MXVR_DMA7_CURR_ADDR            0xFFC02830 /* MXVR Sync Data DMA7 Current Address */
+#define MXVR_DMA7_CURR_COUNT           0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count */
+#define MXVR_AP_CTL                    0xFFC02838 /* MXVR Async Packet Control Register */
+#define MXVR_APRB_START_ADDR           0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
+#define MXVR_APRB_CURR_ADDR            0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
+#define MXVR_APTB_START_ADDR           0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
+#define MXVR_APTB_CURR_ADDR            0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
+#define MXVR_CM_CTL                    0xFFC0284C /* MXVR Control Message Control Register */
+#define MXVR_CMRB_START_ADDR           0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
+#define MXVR_CMRB_CURR_ADDR            0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
+#define MXVR_CMTB_START_ADDR           0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
+#define MXVR_CMTB_CURR_ADDR            0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
+#define MXVR_RRDB_START_ADDR           0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
+#define MXVR_RRDB_CURR_ADDR            0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
+#define MXVR_PAT_DATA_0                0xFFC02868 /* MXVR Pattern Data Register 0 */
+#define MXVR_PAT_EN_0                  0xFFC0286C /* MXVR Pattern Enable Register 0 */
+#define MXVR_PAT_DATA_1                0xFFC02870 /* MXVR Pattern Data Register 1 */
+#define MXVR_PAT_EN_1                  0xFFC02874 /* MXVR Pattern Enable Register 1 */
+#define MXVR_FRAME_CNT_0               0xFFC02878 /* MXVR Frame Counter 0 */
+#define MXVR_FRAME_CNT_1               0xFFC0287C /* MXVR Frame Counter 1 */
+#define MXVR_ROUTING_0                 0xFFC02880 /* MXVR Routing Table Register 0 */
+#define MXVR_ROUTING_1                 0xFFC02884 /* MXVR Routing Table Register 1 */
+#define MXVR_ROUTING_2                 0xFFC02888 /* MXVR Routing Table Register 2 */
+#define MXVR_ROUTING_3                 0xFFC0288C /* MXVR Routing Table Register 3 */
+#define MXVR_ROUTING_4                 0xFFC02890 /* MXVR Routing Table Register 4 */
+#define MXVR_ROUTING_5                 0xFFC02894 /* MXVR Routing Table Register 5 */
+#define MXVR_ROUTING_6                 0xFFC02898 /* MXVR Routing Table Register 6 */
+#define MXVR_ROUTING_7                 0xFFC0289C /* MXVR Routing Table Register 7 */
+#define MXVR_ROUTING_8                 0xFFC028A0 /* MXVR Routing Table Register 8 */
+#define MXVR_ROUTING_9                 0xFFC028A4 /* MXVR Routing Table Register 9 */
+#define MXVR_ROUTING_10                0xFFC028A8 /* MXVR Routing Table Register 10 */
+#define MXVR_ROUTING_11                0xFFC028AC /* MXVR Routing Table Register 11 */
+#define MXVR_ROUTING_12                0xFFC028B0 /* MXVR Routing Table Register 12 */
+#define MXVR_ROUTING_13                0xFFC028B4 /* MXVR Routing Table Register 13 */
+#define MXVR_ROUTING_14                0xFFC028B8 /* MXVR Routing Table Register 14 */
+#define MXVR_BLOCK_CNT                 0xFFC028C0 /* MXVR Block Counter */
+#define MXVR_CLK_CTL                   0xFFC028D0 /* MXVR Clock Control Register */
+#define MXVR_CDRPLL_CTL                0xFFC028D4 /* MXVR Clock/Data Recovery PLL Control Register */
+#define MXVR_FMPLL_CTL                 0xFFC028D8 /* MXVR Frequency Multiply PLL Control Register */
+#define MXVR_PIN_CTL                   0xFFC028DC /* MXVR Pin Control Register */
+#define MXVR_SCLK_CNT                  0xFFC028E0 /* MXVR System Clock Counter Register */
+#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
+#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
+#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
+#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
+#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
+#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
+#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
+#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
+#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
+#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
+#define UART2_LCR                      0xFFC0210C /* Line Control Register */
+#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
+#define UART2_LSR                      0xFFC02114 /* Line Status Register */
+#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
+#define UART2_SCR                      0xFFC0211C /* Scratch Register */
+#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
+#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
+#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+#define USB_FADDR                      0xFFC03C00 /* Function address register */
+#define USB_POWER                      0xFFC03C04 /* Power management register */
+#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03C20 /* USB frame number */
+#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF549_extended__ */
diff --git a/include/asm-blackfin/mach-bf548/BF541_cdef.h b/include/asm-blackfin/mach-bf548/BF541_cdef.h
new file mode 100644
index 0000000000..c0d2a42230
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF541_cdef.h
@@ -0,0 +1,326 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF541_proc__
+#define __BFIN_CDEF_ADSP_BF541_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF542-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF541_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF541_def.h b/include/asm-blackfin/mach-bf548/BF541_def.h
new file mode 100644
index 0000000000..2f9cec696f
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF541_def.h
@@ -0,0 +1,118 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF541_proc__
+#define __BFIN_DEF_ADSP_BF541_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF542-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define DSPID                          0xFFE05000
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+
+#endif /* __BFIN_DEF_ADSP_BF541_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF542_cdef.h b/include/asm-blackfin/mach-bf548/BF542_cdef.h
new file mode 100644
index 0000000000..be48dfd521
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF542_cdef.h
@@ -0,0 +1,326 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF542_proc__
+#define __BFIN_CDEF_ADSP_BF542_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF542-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF542_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h
new file mode 100644
index 0000000000..c2be4de107
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF542_def.h
@@ -0,0 +1,133 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF542_proc__
+#define __BFIN_DEF_ADSP_BF542_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF542-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define DSPID                          0xFFE05000
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF542_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF544_cdef.h b/include/asm-blackfin/mach-bf548/BF544_cdef.h
new file mode 100644
index 0000000000..b3232fcf38
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF544_cdef.h
@@ -0,0 +1,326 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF544_proc__
+#define __BFIN_CDEF_ADSP_BF544_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF544-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF544_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/include/asm-blackfin/mach-bf548/BF544_def.h
new file mode 100644
index 0000000000..834b7a6534
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF544_def.h
@@ -0,0 +1,133 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF544_proc__
+#define __BFIN_DEF_ADSP_BF544_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF544-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define DSPID                          0xFFE05000
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF544_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF547_cdef.h b/include/asm-blackfin/mach-bf548/BF547_cdef.h
new file mode 100644
index 0000000000..e1a1daffb0
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF547_cdef.h
@@ -0,0 +1,326 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF547_proc__
+#define __BFIN_CDEF_ADSP_BF547_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF547-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF547_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/include/asm-blackfin/mach-bf548/BF547_def.h
new file mode 100644
index 0000000000..bb7ae5ecc7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF547_def.h
@@ -0,0 +1,127 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF547_proc__
+#define __BFIN_DEF_ADSP_BF547_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF547-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define DSPID                          0xFFE05000
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF547_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF548_cdef.h b/include/asm-blackfin/mach-bf548/BF548_cdef.h
new file mode 100644
index 0000000000..6cdfbf3d55
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF548_cdef.h
@@ -0,0 +1,326 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF548_proc__
+#define __BFIN_CDEF_ADSP_BF548_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF548-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF548_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/include/asm-blackfin/mach-bf548/BF548_def.h
new file mode 100644
index 0000000000..e72510209e
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF548_def.h
@@ -0,0 +1,133 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF548_proc__
+#define __BFIN_DEF_ADSP_BF548_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF548-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define DSPID                          0xFFE05000
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF548_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF549_cdef.h b/include/asm-blackfin/mach-bf548/BF549_cdef.h
new file mode 100644
index 0000000000..9ac8c2dd46
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF549_cdef.h
@@ -0,0 +1,326 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF549_proc__
+#define __BFIN_CDEF_ADSP_BF549_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF549-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/include/asm-blackfin/mach-bf548/BF549_def.h
new file mode 100644
index 0000000000..f36ecd6ce1
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/BF549_def.h
@@ -0,0 +1,133 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF549_proc__
+#define __BFIN_DEF_ADSP_BF549_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF549-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define DSPID                          0xFFE05000
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF549_proc__ */
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
new file mode 100644
index 0000000000..0451ea7b84
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -0,0 +1,99 @@
+/*
+ * File: include/asm-blackfin/mach-bf548/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file shoule be up to date with:
+ *  - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* False Hardware Error Exception when ISR context is not restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
+/* TWI Slave Boot Mode Is Not Functional */
+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
+/* External FIFO Boot Mode Is Not Functional */
+#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
+/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
+/* Synchronous Burst Flash Boot Mode Is Not Functional */
+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
+/* Host DMA Boot Mode Is Not Functional */
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
+/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
+/* Inadequate Rotary Debounce Logic Duration */
+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
+/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
+/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
+/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
+/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value Is Not Intialized */
+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
+/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
+/* Data Lost when Core Reads SDH Data FIFO */
+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
+/* PLL Status Register Is Inaccurate */
+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* External Memory Read Access Hangs Core With PLL Bypass */
+#define ANOMALY_05000360 (1)
+/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
+#define ANOMALY_05000365 (1)
+/* Addressing Conflict between Boot ROM and Asynchronous Memory */
+#define ANOMALY_05000369 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 1)
+/* Mobile DDR Operation Not Functional */
+#define ANOMALY_05000377 (1)
+/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
+#define ANOMALY_05000378 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000323 (0)
+
+#endif
diff --git a/include/asm-blackfin/mach-bf548/def_local.h b/include/asm-blackfin/mach-bf548/def_local.h
new file mode 100644
index 0000000000..14c111f712
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/def_local.h
@@ -0,0 +1 @@
+#include "ports.h"
diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h
new file mode 100644
index 0000000000..c9bd287187
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/ports.h
@@ -0,0 +1,257 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORTx_MUX Masks */
+#define PORT_x_MUX_0_MASK	0x00000003
+#define PORT_x_MUX_1_MASK	0x0000000C
+#define PORT_x_MUX_2_MASK	0x00000030
+#define PORT_x_MUX_3_MASK	0x000000C0
+#define PORT_x_MUX_4_MASK	0x00000300
+#define PORT_x_MUX_5_MASK	0x00000C00
+#define PORT_x_MUX_6_MASK	0x00003000
+#define PORT_x_MUX_7_MASK	0x0000C000
+#define PORT_x_MUX_8_MASK	0x00030000
+#define PORT_x_MUX_9_MASK	0x000C0000
+#define PORT_x_MUX_10_MASK	0x00300000
+#define PORT_x_MUX_11_MASK	0x00C00000
+#define PORT_x_MUX_12_MASK	0x03000000
+#define PORT_x_MUX_13_MASK	0x0C000000
+#define PORT_x_MUX_14_MASK	0x30000000
+#define PORT_x_MUX_15_MASK	0xC0000000
+
+#define PORT_x_MUX_FUNC_1	(0x0)
+#define PORT_x_MUX_FUNC_2	(0x1)
+#define PORT_x_MUX_FUNC_3	(0x2)
+#define PORT_x_MUX_FUNC_4	(0x3)
+#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
+#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
+#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
+#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
+#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
+#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
+#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
+#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
+#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
+#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
+#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
+#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
+#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
+#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
+#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
+#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
+#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
+#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
+#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
+#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
+#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
+#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
+#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
+#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
+#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
+#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
+#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
+#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
+#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+
+/* Port A Masks */
+#define PA0			0x0001
+#define PA1			0x0002
+#define PA2			0x0004
+#define PA3			0x0008
+#define PA4			0x0010
+#define PA5			0x0020
+#define PA6			0x0040
+#define PA7			0x0080
+#define PA8			0x0100
+#define PA9			0x0200
+#define PA10			0x0400
+#define PA11			0x0800
+#define PA12			0x1000
+#define PA13			0x2000
+#define PA14			0x4000
+#define PA15			0x8000
+
+/* Port B Masks */
+#define PB0			0x0001
+#define PB1			0x0002
+#define PB2			0x0004
+#define PB3			0x0008
+#define PB4			0x0010
+#define PB5			0x0020
+#define PB6			0x0040
+#define PB7			0x0080
+#define PB8			0x0100
+#define PB9			0x0200
+#define PB10			0x0400
+#define PB11			0x0800
+#define PB12			0x1000
+#define PB13			0x2000
+#define PB14			0x4000
+#define PB15			0x8000
+
+/* Port C Masks */
+#define PC0			0x0001
+#define PC1			0x0002
+#define PC2			0x0004
+#define PC3			0x0008
+#define PC4			0x0010
+#define PC5			0x0020
+#define PC6			0x0040
+#define PC7			0x0080
+#define PC8			0x0100
+#define PC9			0x0200
+#define PC10			0x0400
+#define PC11			0x0800
+#define PC12			0x1000
+#define PC13			0x2000
+#define PC14			0x4000
+#define PC15			0x8000
+
+/* Port F Masks */
+#define PD0			0x0001
+#define PD1			0x0002
+#define PD2			0x0004
+#define PD3			0x0008
+#define PD4			0x0010
+#define PD5			0x0020
+#define PD6			0x0040
+#define PD7			0x0080
+#define PD8			0x0100
+#define PD9			0x0200
+#define PD10			0x0400
+#define PD11			0x0800
+#define PD12			0x1000
+#define PD13			0x2000
+#define PD14			0x4000
+#define PD15			0x8000
+
+/* Port F Masks */
+#define PE0			0x0001
+#define PE1			0x0002
+#define PE2			0x0004
+#define PE3			0x0008
+#define PE4			0x0010
+#define PE5			0x0020
+#define PE6			0x0040
+#define PE7			0x0080
+#define PE8			0x0100
+#define PE9			0x0200
+#define PE10			0x0400
+#define PE11			0x0800
+#define PE12			0x1000
+#define PE13			0x2000
+#define PE14			0x4000
+#define PE15			0x8000
+
+/* Port F Masks */
+#define PF0			0x0001
+#define PF1			0x0002
+#define PF2			0x0004
+#define PF3			0x0008
+#define PF4			0x0010
+#define PF5			0x0020
+#define PF6			0x0040
+#define PF7			0x0080
+#define PF8			0x0100
+#define PF9			0x0200
+#define PF10			0x0400
+#define PF11			0x0800
+#define PF12			0x1000
+#define PF13			0x2000
+#define PF14			0x4000
+#define PF15			0x8000
+
+/* Port G Masks */
+#define PG0			0x0001
+#define PG1			0x0002
+#define PG2			0x0004
+#define PG3			0x0008
+#define PG4			0x0010
+#define PG5			0x0020
+#define PG6			0x0040
+#define PG7			0x0080
+#define PG8			0x0100
+#define PG9			0x0200
+#define PG10			0x0400
+#define PG11			0x0800
+#define PG12			0x1000
+#define PG13			0x2000
+#define PG14			0x4000
+#define PG15			0x8000
+
+/* Port H Masks */
+#define PH0			0x0001
+#define PH1			0x0002
+#define PH2			0x0004
+#define PH3			0x0008
+#define PH4			0x0010
+#define PH5			0x0020
+#define PH6			0x0040
+#define PH7			0x0080
+#define PH8			0x0100
+#define PH9			0x0200
+#define PH10			0x0400
+#define PH11			0x0800
+#define PH12			0x1000
+#define PH13			0x2000
+#define PH14			0x4000
+#define PH15			0x8000
+
+/* Port J Masks */
+#define PJ0			0x0001
+#define PJ1			0x0002
+#define PJ2			0x0004
+#define PJ3			0x0008
+#define PJ4			0x0010
+#define PJ5			0x0020
+#define PJ6			0x0040
+#define PJ7			0x0080
+#define PJ8			0x0100
+#define PJ9			0x0200
+#define PJ10			0x0400
+#define PJ11			0x0800
+#define PJ12			0x1000
+#define PJ13			0x2000
+#define PJ14			0x4000
+#define PJ15			0x8000
+
+#endif