diff options
| author | Aubrey.Li <aubrey.adi@gmail.com> | 2007-03-09 13:38:44 +0800 |
|---|---|---|
| committer | Aubrey.Li <aubrey.adi@gmail.com> | 2007-03-09 13:38:44 +0800 |
| commit | 3f0606ad0b5639f7f22848fe5b4574e754d0470f (patch) | |
| tree | 3cb4fd316134b6a176607ad61739720aeb971a5a /include/asm-blackfin/mem_init.h | |
| parent | eb92f613556800f7483666db09d9a237ad911d4a (diff) | |
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support
Diffstat (limited to 'include/asm-blackfin/mem_init.h')
| -rw-r--r-- | include/asm-blackfin/mem_init.h | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h index 1a13d908e0..a9baacdfb8 100644 --- a/include/asm-blackfin/mem_init.h +++ b/include/asm-blackfin/mem_init.h @@ -22,7 +22,13 @@ * MA 02111-1307 USA */ -#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E ) +#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \ + CONFIG_MEM_MT48LC64M4A2FB_7E || \ + CONFIG_MEM_MT48LC16M8A2TG_75 || \ + CONFIG_MEM_MT48LC8M16A2TG_7E || \ + CONFIG_MEM_MT48LC8M32B2B5_7 || \ + CONFIG_MEM_MT48LC32M8A2_75) + #if ( CONFIG_SCLK_HZ > 119402985 ) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -66,7 +72,7 @@ #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) #define SDRAM_tRP TRP_1 #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_4 + #define SDRAM_tRAS TRAS_3 #define SDRAM_tRAS_num 3 #define SDRAM_tRCD TRCD_1 #define SDRAM_tWR TWR_2 @@ -111,6 +117,34 @@ #define SDRAM_CL CL_2 #endif +#if (CONFIG_MEM_MT48LC16M8A2TG_75) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 +#endif + +#if (CONFIG_MEM_MT48LC32M8A2_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + +#if (CONFIG_MEM_MT48LC8M16A2TG_7E) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_2 +#endif + +#if (CONFIG_MEM_MT48LC8M32B2B5_7) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 +#endif + #if ( CONFIG_MEM_SIZE == 128 ) #define SDRAM_SIZE EBSZ_128 #endif |