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authorPeter Tyser <ptyser@xes-inc.com>2010-04-12 22:28:08 -0500
committerWolfgang Denk <wd@denx.de>2010-04-13 09:13:12 +0200
commit819833af39a91fa1c1e8252862bbda6f5a602f7b (patch)
treed5c9d1628643347ab2b5a8085acfa6f96709fda3 /include/asm-ppc/fsl_ddr_dimm_params.h
parent61f2b38a17f5b21c59f2afe6cf1cbb5f28638cf9 (diff)
Move architecture-specific includes to arch/$ARCH/include/asm
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'include/asm-ppc/fsl_ddr_dimm_params.h')
-rw-r--r--include/asm-ppc/fsl_ddr_dimm_params.h91
1 files changed, 0 insertions, 91 deletions
diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h
deleted file mode 100644
index 55923e09b3..0000000000
--- a/include/asm-ppc/fsl_ddr_dimm_params.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef DDR2_DIMM_PARAMS_H
-#define DDR2_DIMM_PARAMS_H
-
-/* Parameters for a DDR2 dimm computed from the SPD */
-typedef struct dimm_params_s {
-
- /* DIMM organization parameters */
- char mpart[19]; /* guaranteed null terminated */
-
- unsigned int n_ranks;
- unsigned long long rank_density;
- unsigned long long capacity;
- unsigned int data_width;
- unsigned int primary_sdram_width;
- unsigned int ec_sdram_width;
- unsigned int registered_dimm;
-
- /* SDRAM device parameters */
- unsigned int n_row_addr;
- unsigned int n_col_addr;
- unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
- unsigned int n_banks_per_sdram_device;
- unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
- unsigned int row_density;
-
- /* used in computing base address of DIMMs */
- unsigned long long base_address;
- /* mirrored DIMMs */
- unsigned int mirrored_dimm; /* only for ddr3 */
-
- /* DIMM timing parameters */
-
- unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
- unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */
- unsigned int tFAW_ps; /* four active window delay, only for ddr3 */
-
- /*
- * SDRAM clock periods
- * The range for these are 1000-10000 so a short should be sufficient
- */
- unsigned int tCKmin_X_ps;
- unsigned int tCKmin_X_minus_1_ps;
- unsigned int tCKmin_X_minus_2_ps;
- unsigned int tCKmax_ps;
-
- /* SPD-defined CAS latencies */
- unsigned int caslat_X;
- unsigned int caslat_X_minus_1;
- unsigned int caslat_X_minus_2;
-
- unsigned int caslat_lowest_derated; /* Derated CAS latency */
-
- /* basic timing parameters */
- unsigned int tRCD_ps;
- unsigned int tRP_ps;
- unsigned int tRAS_ps;
-
- unsigned int tWR_ps; /* maximum = 63750 ps */
- unsigned int tWTR_ps; /* maximum = 63750 ps */
- unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
- = 511750 ps */
-
- unsigned int tRRD_ps; /* maximum = 63750 ps */
- unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
-
- unsigned int refresh_rate_ps;
-
- /* DDR3 doesn't need these as below */
- unsigned int tIS_ps; /* byte 32, spd->ca_setup */
- unsigned int tIH_ps; /* byte 33, spd->ca_hold */
- unsigned int tDS_ps; /* byte 34, spd->data_setup */
- unsigned int tDH_ps; /* byte 35, spd->data_hold */
- unsigned int tRTP_ps; /* byte 38, spd->trtp */
- unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
- unsigned int tQHS_ps; /* byte 45, spd->tqhs */
-} dimm_params_t;
-
-extern unsigned int ddr_compute_dimm_parameters(
- const generic_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number);
-
-#endif