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authorVignesh R <vigneshr@ti.com>2016-12-21 10:42:32 +0530
committerJagan Teki <jagan@openedev.com>2017-01-04 16:38:12 +0100
commit57897c13de03ac0136d64641a3eab526c6810387 (patch)
tree1449b0c095cc64911392faf76b8e86a8e194feee /include/bedbug
parent87f5f5417fc897df0b05826b408f0f4b7d2ee388 (diff)
spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
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