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| author | Kever Yang <kever.yang@rock-chips.com> | 2019-10-18 15:54:16 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-11-10 20:40:20 +0800 |
| commit | 6024467bcc0e38fb5f1d2d80b73e770c94e4530c (patch) | |
| tree | 585fb3a3eba902fce52687f7e8c224f3d7228c20 /include/bitfield.h | |
| parent | 006ab58d4636124f617174fa2dfe24739874ee91 (diff) | |
rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to
limit the SPL size in 0x40000(start from 0) so that we don't need to do
the relocate for ATF loading.
Note that there will be separate BSS, STACK and MALLOC heap, so the size
0x40000(256KB) should be enough for SPL text.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'include/bitfield.h')
0 files changed, 0 insertions, 0 deletions