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authorSimon Glass <sjg@chromium.org>2019-10-21 17:26:51 -0600
committerSimon Glass <sjg@chromium.org>2019-10-27 10:56:51 -0600
commit5256beecb8a14efba805a2f3f14afb33752ac71a (patch)
tree57ca586bf1bfa02d7653801595663ba3649ec7a5 /include/bootstage.h
parentac9cd4805c8b11f529b508921c2275b889265313 (diff)
bootstage: Mark the start/end of TPL and SPL separately
At present bootstage in TPL and SPL use the same ID so it is not possible to see the timing of each. Separate out the IDs and use the correct one depending on which phase we are at. Example output: Timer summary in microseconds (14 records): Mark Elapsed Stage 0 0 reset 224,787 224,787 TPL 282,248 57,461 end TPL 341,067 58,819 SPL 925,436 584,369 end SPL 931,710 6,274 board_init_f 1,035,482 103,772 board_init_r 1,387,852 352,370 main_loop 1,387,911 59 id=175 Accumulated time: 196 dm_r 8,300 dm_spl 14,139 dm_f 229,121 fsp-m 262,992 fsp-s Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/bootstage.h')
-rw-r--r--include/bootstage.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/bootstage.h b/include/bootstage.h
index 5e7e242b83..d105ae0181 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -170,6 +170,8 @@ enum bootstage_id {
* rough boot timing information.
*/
BOOTSTAGE_ID_AWAKE,
+ BOOTSTAGE_ID_START_TPL,
+ BOOTSTAGE_ID_END_TPL,
BOOTSTAGE_ID_START_SPL,
BOOTSTAGE_ID_END_SPL,
BOOTSTAGE_ID_START_UBOOT_F,