diff options
| author | wdenk <wdenk> | 2004-06-06 21:35:06 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-06-06 21:35:06 +0000 |
| commit | 1114257c9df3fa3db39ff55dd03d1f7cbc5c0603 (patch) | |
| tree | 7d62ed142cf3c00aea35e518ed28dc9f5c6887fd /include/configs/DUET_ADS.h | |
| parent | d7a04603ae9c85d496b3991f29dbb8ea339ace49 (diff) | |
Patch by Yuli Barcohen, 19 Apr 2004:
- Rename DUET_ADS to MPC885ADS
- Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
- Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
- Clean up FADS family port to use the new defines
Diffstat (limited to 'include/configs/DUET_ADS.h')
| -rw-r--r-- | include/configs/DUET_ADS.h | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/include/configs/DUET_ADS.h b/include/configs/DUET_ADS.h deleted file mode 100644 index 8a4025797d..0000000000 --- a/include/configs/DUET_ADS.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola DUET ADS board. Values common to all FADS family boards - * are in board/fads/fads.h - * - * Copyright (C) 2003 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board type */ -#define CONFIG_DUET_ADS 1 /* Duet (MPC87x/88x) ADS */ -#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ - -#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 - -#define CFG_8XX_FACT 5 /* Multiply by 5 */ -#define CFG_8XX_XIN 10000000 /* 10 MHz in */ - -#define CONFIG_SDRAM_50MHZ 1 - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control - */ -#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) - -#include "fads.h" - -#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) - -#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) - -#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) - -#define BCSR5_MII2_EN 0x40 -#define BCSR5_MII2_RST 0x20 -#define BCSR5_T1_RST 0x10 -#define BCSR5_ATM155_RST 0x08 -#define BCSR5_ATM25_RST 0x04 -#define BCSR5_MII1_EN 0x02 -#define BCSR5_MII1_RST 0x01 - -#endif /* __CONFIG_H */ |