diff options
| author | wdenk <wdenk> | 2004-01-04 16:28:35 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-01-04 16:28:35 +0000 |
| commit | 180d3f74e4738ee107e269cbb949481075dd789a (patch) | |
| tree | ce40863d3e1b3ff07a5027d788ff1fdb5416d0d7 /include/configs/DUET_ADS.h | |
| parent | dd875c767e6fb0f4fecfb799b706d84562a7acee (diff) | |
* Fix problems caused by Robert Schwebel's cramfs patch
* Patch by Scott McNutt, 02 Jan 2004:
Add support for the Nios Active Serial Memory Interface (ASMI)
on Cyclone devices
* Patch by Andrea Marson, 16 Dec 2003:
Add support for the PPChameleon ME and HI modules
* Patch by Yuli Barcohen, 22 Dec 2003:
Add support for Motorola DUET ADS board (MPC87x/88x)
Diffstat (limited to 'include/configs/DUET_ADS.h')
| -rw-r--r-- | include/configs/DUET_ADS.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/include/configs/DUET_ADS.h b/include/configs/DUET_ADS.h new file mode 100644 index 0000000000..8a4025797d --- /dev/null +++ b/include/configs/DUET_ADS.h @@ -0,0 +1,53 @@ +/* + * A collection of structures, addresses, and values associated with + * the Motorola DUET ADS board. Values common to all FADS family boards + * are in board/fads/fads.h + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Board type */ +#define CONFIG_DUET_ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ + +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 38400 + +#define CFG_8XX_FACT 5 /* Multiply by 5 */ +#define CFG_8XX_XIN 10000000 /* 10 MHz in */ + +#define CONFIG_SDRAM_50MHZ 1 + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control + */ +#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) + +#include "fads.h" + +#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) + +#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) + +#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) + +#define BCSR5_MII2_EN 0x40 +#define BCSR5_MII2_RST 0x20 +#define BCSR5_T1_RST 0x10 +#define BCSR5_ATM155_RST 0x08 +#define BCSR5_ATM25_RST 0x04 +#define BCSR5_MII1_EN 0x02 +#define BCSR5_MII1_RST 0x01 + +#endif /* __CONFIG_H */ |