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authorMario Six <mario.six@gdsys.cc>2019-01-21 09:18:03 +0100
committerMario Six <mario.six@gdsys.cc>2019-05-21 07:52:33 +0200
commitfe7d654d04a4ba87813dcf8acb7a17373029770d (patch)
treeacff08e60a356274b602f42d44a975b7a279eca2 /include/configs/MPC8313ERDB_NAND.h
parentdaac2086ce1a36ffbd603eb643f45d14faae40e7 (diff)
mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig
Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/MPC8313ERDB_NAND.h')
-rw-r--r--include/configs/MPC8313ERDB_NAND.h14
1 files changed, 0 insertions, 14 deletions
diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index 40b0264dbe..93b553c905 100644
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -219,14 +219,6 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-/* NAND */
-#define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
-
-/* FLASH */
-#define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
-
/* Still needed for spl_minimal.c */
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
@@ -235,9 +227,6 @@
#define CONFIG_SYS_BCSR_ADDR 0xFA000000
#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
/* map at 0xFA000000 on LCS3 */
-/* BCSR */
-#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* Vitesse 7385 */
@@ -247,9 +236,6 @@
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-/* VSC7385 */
-#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#endif