summaryrefslogtreecommitdiff
path: root/include/configs/MPC832XEMDS.h
diff options
context:
space:
mode:
authorMario Six <mario.six@gdsys.cc>2019-01-21 09:18:01 +0100
committerMario Six <mario.six@gdsys.cc>2019-05-21 07:52:33 +0200
commita8f975391f2452bc7a51eeafd030c85c32e1aca5 (patch)
tree8b5bc02ac3891c277a8cae70dcf951f86c705f65 /include/configs/MPC832XEMDS.h
parent87ee51048eae94eb5c075b6c900d4da5e9531cf4 (diff)
mpc83xx: Simplify BR,OR lines
Re-format all BR,OR #define lines into single lines. This makes them harder to read, but accessible to semi-automatic replacement. Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/MPC832XEMDS.h')
-rw-r--r--include/configs/MPC832XEMDS.h70
1 files changed, 14 insertions, 56 deletions
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 3a8a3e4fb8..41b0223135 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -133,20 +133,9 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfe006ff7 */
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -159,19 +148,9 @@
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
+/* BCSR */
+#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/*
* Windows to access PIB via local bus
@@ -183,39 +162,18 @@
/*
* CS2 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
+
+/* PIB1 */
+#define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/*
* CS3 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
- CONFIG_SYS_PIB_WINDOW_SIZE) \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
+
+/* PIB2 */
+#define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/*
* Serial Port