diff options
| author | Joe Hershberger <joe.hershberger@ni.com> | 2011-10-11 23:57:30 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2011-11-03 18:27:56 -0500 |
| commit | 7d6a098219f8473ca4653cce5f7a49672b967f36 (patch) | |
| tree | 82ad07513347a36c90f81ce50dbad8a5ca8c229e /include/configs/MPC837XEMDS.h | |
| parent | 2fef402097866b4172d7a966a72397a5ccba5b10 (diff) | |
mpc83xx: Cleanup usage of LBC constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/configs/MPC837XEMDS.h')
| -rw-r--r-- | include/configs/MPC837XEMDS.h | 44 |
1 files changed, 28 insertions, 16 deletions
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 8c2af084a1..d7ee405636 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -243,19 +243,20 @@ /* Window base at flash base */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | (2 << BR_PS_SHIFT) /* 16 bit port */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EHTR \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFE000FF7 */ @@ -272,11 +273,22 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ - - /* Port size=8bit, MSEL=GPCM */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) -#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF8000801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFFE9F7 */ /* * NAND Flash on the Local Bus @@ -286,13 +298,13 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CONFIG_SYS_NAND_BASE 0xE0600000 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* 8 bit port */ \ | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR3_PRELIM (0xFFFF8000 /* length 32K */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | OR_FCM_BCTLD \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -303,7 +315,7 @@ /* 0xFFFF919E */ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) /* * Serial Port |