diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2011-01-04 17:57:59 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:21 -0600 |
| commit | 8b47d7ec9bbb7c3022aa758a971acb7335ea1cdf (patch) | |
| tree | 65e47d2d0b27aba54751ca15be6536f5743b218a /include/configs/MPC8548CDS.h | |
| parent | a09b9b68d492e978ef0e14cae93ff9cfbc2d3e4b (diff) | |
powerpc/85xx: Convert MPC8548CDS to use common SRIO init code
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8548CDS.h')
| -rw-r--r-- | include/configs/MPC8548CDS.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4c5b998423..ececa3875f 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007, 2010 Freescale Semiconductor. + * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -40,10 +40,12 @@ #define CONFIG_SYS_TEXT_BASE 0xfff80000 #endif +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#undef CONFIG_RIO #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ @@ -364,14 +366,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif -#ifdef CONFIG_RIO /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ -#endif +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #ifdef CONFIG_LEGACY #define BRIDGE_ID 17 |