diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2008-10-03 11:46:59 -0400 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-10-07 16:22:22 -0500 |
| commit | 1f3ba317a5c5f3a7aabf580fddc211f4bb5a4540 (patch) | |
| tree | 1d1528b1215a191e6b347c8302f116d858406b55 /include/configs/MPC8572DS.h | |
| parent | c0391111c33c22fabeddf8f4ca801ec7645b4f5c (diff) | |
Minor fixes for I2C address on MPC8572DS
MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'include/configs/MPC8572DS.h')
| -rw-r--r-- | include/configs/MPC8572DS.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index d7e3a887cf..87b10116d1 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -108,6 +108,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ +#define CFG_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ @@ -293,11 +294,14 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3100 +#define CFG_I2C_NOPROBES {0,0x29} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 /* * General PCI |