diff options
| author | Timur Tabi <timur@freescale.com> | 2010-03-29 12:51:07 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-03-30 10:50:22 -0500 |
| commit | 9ff32d8ccf0e23b5577c25610f001af8d761b4a2 (patch) | |
| tree | 43cce2d1c3caf0a05fdbb33f6a44855f4965433f /include/configs/MPC8610HPCD.h | |
| parent | 33f57bd553edf29dffef5a6c7d76e169c79a6049 (diff) | |
mpc86xx: set the DDR BATs after calculating true DDR size
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way. If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).
Currently we are limited to power of two sized DDR since we only use a
single bat. If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8610HPCD.h')
| -rw-r--r-- | include/configs/MPC8610HPCD.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1d2d659239..fed441eb37 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -341,10 +341,8 @@ * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U +#define CONFIG_SYS_DBAT0L (BATL_PP_RW) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW) /* * BAT1 1G Cache-inhibited, guarded |