Merge commit 'wd/master'

1 files changed, 127 insertions, 126 deletions

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index d7a7f9087f..455e154222 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -36,11 +36,11 @@
 #define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
-#define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
-#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
+#define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 
 #ifdef RUN_DIAG
-#define CFG_DIAG_ADDR        0xff800000
+#define CFG_DIAG_ADDR	     0xff800000
 #endif
 
 #define CFG_RESET_ADDRESS    0xfff00100
@@ -51,7 +51,7 @@
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
 
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
@@ -61,14 +61,15 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_NUM_DDR_CONTROLLERS     2
-/* #define CONFIG_DDR_INTERLEAVE               1 */
+/* #define CONFIG_DDR_INTERLEAVE	       1 */
 #define CACHE_LINE_INTERLEAVING		0x20000000
 #define PAGE_INTERLEAVING		0x21000000
 #define BANK_INTERLEAVING		0x22000000
 #define SUPER_BANK_INTERLEAVING		0x23000000
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
 
-#define CONFIG_ALTIVEC          1
+#define CONFIG_ALTIVEC		1
 
 /*
  * L2CR setup -- make sure this is right for your board!
@@ -81,7 +82,7 @@
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
-#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
 #endif
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
@@ -93,7 +94,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
@@ -126,18 +127,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
     #define CFG_SDRAM_SIZE	256		/* DDR is 256MB */
 
     #define CFG_DDR_CS0_BNDS	0x0000000F
-    #define CFG_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
+    #define CFG_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
     #define CFG_DDR_EXT_REFRESH 0x00000000
-    #define CFG_DDR_TIMING_0    0x00260802
+    #define CFG_DDR_TIMING_0	0x00260802
     #define CFG_DDR_TIMING_1	0x39357322
     #define CFG_DDR_TIMING_2	0x14904cc8
     #define CFG_DDR_MODE_1	0x00480432
     #define CFG_DDR_MODE_2	0x00000000
     #define CFG_DDR_INTERVAL	0x06090100
-    #define CFG_DDR_DATA_INIT   0xdeadbeef
-    #define CFG_DDR_CLK_CTRL    0x03800000
-    #define CFG_DDR_OCD_CTRL    0x00000000
-    #define CFG_DDR_OCD_STATUS  0x00000000
+    #define CFG_DDR_DATA_INIT	0xdeadbeef
+    #define CFG_DDR_CLK_CTRL	0x03800000
+    #define CFG_DDR_OCD_CTRL	0x00000000
+    #define CFG_DDR_OCD_STATUS	0x00000000
     #define CFG_DDR_CONTROL	0xe3008000	/* Type = DDR2 */
     #define CFG_DDR_CONTROL2	0x04400000
 
@@ -169,7 +170,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  *
  * Note that, on switching the boot location, fef00000 becomes fff00000.
  */
-#define CFG_FLASH_BASE          0xfe800000     /* start of FLASH 32M */
+#define CFG_FLASH_BASE		0xfe800000     /* start of FLASH 32M */
 #define CFG_FLASH_BASE2		0xff800000
 
 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
@@ -188,7 +189,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xf8100000      /* PIXIS registers */
+#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
@@ -203,7 +204,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CFG_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
+#define CFG_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
 
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
 #define CFG_MAX_FLASH_SECT	128		/* sectors per device */
@@ -211,7 +212,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -220,7 +221,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef	CFG_RAMBOOT
 #endif
 
 #if defined(CFG_RAMBOOT)
@@ -237,32 +238,32 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #else
 #define CFG_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
 #endif
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(1024 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_REG_SIZE	1
 #define CFG_NS16550_CLK		get_bus_freq(0)
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
@@ -285,7 +286,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
 #define CFG_I2C_OFFSET		0x3100
 
 /*
@@ -307,13 +308,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 /* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x80000000
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
 
 /* For RTL8139 */
 #define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
-#define _IO_BASE                0x00000000
+#define _IO_BASE		0x00000000
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
@@ -324,12 +325,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_PCI)
 
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
 #undef CFG_SCSI_SCAN_BUS_REVERSE
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #define CONFIG_RTL8139
 
@@ -339,19 +340,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /************************************************************
  * USB support
  ************************************************************/
-#define CONFIG_PCI_OHCI		1
+#define CONFIG_PCI_OHCI			1
 #define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_USB_KEYBOARD	1
+#define CONFIG_USB_KEYBOARD		1
 #define CFG_DEVICE_DEREGISTER
-#define CFG_USB_EVENT_POLL	1
-#define CFG_USB_OHCI_SLOT_NAME 	"ohci_pci"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_USB_EVENT_POLL		1
+#define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
 #define CFG_OHCI_SWAP_REG_ACCESS	1
 
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 /*PCIE video card used*/
@@ -383,7 +384,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SATA_ULI5288
 #define CFG_SCSI_MAX_SCSI_ID	4
 #define CFG_SCSI_MAX_LUN	1
-#define CFG_SCSI_MAX_DEVICE 	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 #define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
 #endif
 
@@ -394,19 +395,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
 
-#define CONFIG_TSEC1    1
-#define CONFIG_TSEC1_NAME       "eTSEC1"
-#define CONFIG_TSEC2    1
-#define CONFIG_TSEC2_NAME       "eTSEC2"
-#define CONFIG_TSEC3    1
-#define CONFIG_TSEC3_NAME       "eTSEC3"
-#define CONFIG_TSEC4    1
-#define CONFIG_TSEC4_NAME       "eTSEC4"
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC4		1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
 
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -426,76 +427,76 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif	/* CONFIG_TSEC_ENET */
 
 /*
- * BAT0         2G     Cacheable, non-guarded
- * 0x0000_0000  2G     DDR
+ * BAT0		2G     Cacheable, non-guarded
+ * 0x0000_0000	2G     DDR
  */
-#define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CFG_IBAT0U      CFG_DBAT0U
+#define CFG_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U	CFG_DBAT0U
 
 /*
- * BAT1         1G     Cache-inhibited, guarded
- * 0x8000_0000  512M   PCI-Express 1 Memory
- * 0xa000_0000  512M   PCI-Express 2 Memory
+ * BAT1		1G     Cache-inhibited, guarded
+ * 0x8000_0000	512M   PCI-Express 1 Memory
+ * 0xa000_0000	512M   PCI-Express 2 Memory
  *	Changed it for operating from 0xd0000000
  */
-#define CFG_DBAT1L      ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
+#define CFG_DBAT1L	( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT1U	(CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
 #define CFG_IBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U      CFG_DBAT1U
+#define CFG_IBAT1U	CFG_DBAT1U
 
 /*
- * BAT2         512M   Cache-inhibited, guarded
- * 0xc000_0000  512M   RapidIO Memory
+ * BAT2		512M   Cache-inhibited, guarded
+ * 0xc000_0000	512M   RapidIO Memory
  */
-#define CFG_DBAT2L      (CFG_RIO_MEM_PHYS | BATL_PP_RW \
+#define CFG_DBAT2L	(CFG_RIO_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT2U	(CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 #define CFG_IBAT2L	(CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U      CFG_DBAT2U
+#define CFG_IBAT2U	CFG_DBAT2U
 
 /*
- * BAT3         4M     Cache-inhibited, guarded
- * 0xf800_0000  4M     CCSR
+ * BAT3		4M     Cache-inhibited, guarded
+ * 0xf800_0000	4M     CCSR
  */
-#define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
+#define CFG_DBAT3L	( CFG_CCSRBAR | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U      CFG_DBAT3U
+#define CFG_DBAT3U	(CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	CFG_DBAT3U
 
 /*
- * BAT4         32M    Cache-inhibited, guarded
- * 0xe200_0000  16M    PCI-Express 1 I/O
- * 0xe300_0000  16M    PCI-Express 2 I/0
+ * BAT4		32M    Cache-inhibited, guarded
+ * 0xe200_0000	16M    PCI-Express 1 I/O
+ * 0xe300_0000	16M    PCI-Express 2 I/0
  *    Note that this is at 0xe0000000
  */
-#define CFG_DBAT4L      ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
+#define CFG_DBAT4L	( CFG_PCI1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT4U	(CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 #define CFG_IBAT4L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U      CFG_DBAT4U
+#define CFG_IBAT4U	CFG_DBAT4U
 
 /*
- * BAT5         128K   Cacheable, non-guarded
- * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
+ * BAT5		128K   Cacheable, non-guarded
+ * 0xe401_0000	128K   Init RAM for stack in the CPU DCache (no backing memory)
  */
-#define CFG_DBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_IBAT5L      CFG_DBAT5L
-#define CFG_IBAT5U      CFG_DBAT5U
+#define CFG_DBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L	CFG_DBAT5L
+#define CFG_IBAT5U	CFG_DBAT5U
 
 /*
- * BAT6         32M    Cache-inhibited, guarded
- * 0xfe00_0000  32M    FLASH
+ * BAT6		32M    Cache-inhibited, guarded
+ * 0xfe00_0000	32M    FLASH
  */
-#define CFG_DBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+#define CFG_DBAT6L	((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U      ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U      CFG_DBAT6U
+#define CFG_DBAT6U	((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L	((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	CFG_DBAT6U
 
 #define CFG_DBAT7L 0x00000000
 #define CFG_DBAT7U 0x00000000
@@ -556,7 +557,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING          /* Command-line editing */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CFG_LOAD_ADDR	0x2000000	/* default load address */
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 
@@ -597,7 +598,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR   00:E0:0C:00:00:01
+#define CONFIG_ETHADDR	 00:E0:0C:00:00:01
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
@@ -623,45 +624,45 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_LOADADDR		1000000
 
 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
-#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
 
-#define	CONFIG_EXTRA_ENV_SETTINGS				        \
-   "netdev=eth0\0"                                                      \
-   "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
-   "tftpflash=tftpboot $loadaddr $uboot; " 			\
-	"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
-	"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
-	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
-	"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
-	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
-   "consoledev=ttyS0\0"                                                 \
-   "ramdiskaddr=2000000\0"						\
-   "ramdiskfile=your.ramdisk.u-boot\0"                                  \
-   "fdtaddr=c00000\0"						\
-   "fdtfile=mpc8641_hpcn.dtb\0"                                  \
-   "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-   "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
-   "maxcpus=2"
-
-
-#define CONFIG_NFSBOOTCOMMAND	                                        \
-   "setenv bootargs root=/dev/nfs rw "                                  \
-      "nfsroot=$serverip:$rootpath "                                    \
-      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"                                          \
-   "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
-   "setenv bootargs root=/dev/ram rw "                                  \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $ramdiskaddr $ramdiskfile;"                                    \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"                                          \
-   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=2000000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=c00000\0"						\
+	"fdtfile=mpc8641_hpcn.dtb\0"					\
+	"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+	"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+	"maxcpus=2"
+
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	      "nfsroot=$serverip:$rootpath "				\
+	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	      "console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	      "console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND