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authorJon Loeliger <jdl@jdl.com>2006-05-19 13:26:34 -0500
committerJon Loeliger <jdl@jdl.com>2006-05-19 13:54:02 -0500
commit9a655876e5995be80f49054e2509500e871e4d3a (patch)
treefba8b9957695225f404ee8814b43aad846e9c660 /include/configs/MPC8641HPCN.h
parent586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c (diff)
Enable dual DDR controllers and interleaving.
Diffstat (limited to 'include/configs/MPC8641HPCN.h')
-rw-r--r--include/configs/MPC8641HPCN.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index aaf99c150f..2a197be294 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -57,6 +57,13 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+/* #define CONFIG_DDR_INTERLEAVE 1 */
+#define CACHE_LINE_INTERLEAVING 0x20000000
+#define PAGE_INTERLEAVING 0x21000000
+#define BANK_INTERLEAVING 0x22000000
+#define SUPER_BANK_INTERLEAVING 0x23000000
+
#define CONFIG_ALTIVEC 1
@@ -99,7 +106,10 @@
/*
* Determine DDR configuration from I2C interface.
*/
- #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
#else
/*