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authorKumar Gala <galak@kernel.crashing.org>2011-01-31 22:18:47 -0600
committerKumar Gala <galak@kernel.crashing.org>2011-04-04 09:24:41 -0500
commitc39f44dc6f5ae843d5def511f6e71d4b012dc598 (patch)
treed863c3a3e87967d01e4de1021bd20abe3b57af7a /include/configs/P2020DS.h
parent5df4b0ad0dff3cef1bd6660bcc8cba028c80adcb (diff)
powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/P2020DS.h')
-rw-r--r--include/configs/P2020DS.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 6648d6ea47..1815191f59 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -130,7 +130,7 @@
/* I2C addresses of SPD EEPROMs */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
-#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */