diff options
| author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2008-01-08 11:13:09 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-01-09 06:32:23 +0100 |
| commit | 7d5d75633174867316a0c0f2fca5ceb2cf312cde (patch) | |
| tree | 551fbdce49f54eded8623ef3295991799e97705c /include/configs/PMC440.h | |
| parent | 802b769bac17b0560d3535a42c502469ee190cd1 (diff) | |
ppc4xx: Disable error message when no NAND chip is installed on PMC440
Add CFG_NAND_QUIET_TEST option to disable error message when
no NAND chip is installed on PMC440 boards.
Disable a couple of config defines that are only used for NAND_U_BOOT.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Diffstat (limited to 'include/configs/PMC440.h')
| -rw-r--r-- | include/configs/PMC440.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 3d2ed1e7d6..87fca3c470 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -167,6 +167,7 @@ * set up. While still running from cache, I experienced problems accessing * the NAND controller. sr - 2006-08-25 */ +#if defined (CONFIG_NAND_U_BOOT) #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ #define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ @@ -195,6 +196,7 @@ #define CFG_NAND_OOBSIZE 16 #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} +#endif #ifdef CFG_ENV_IS_IN_NAND /* @@ -501,6 +503,7 @@ #define NAND_MAX_CHIPS 1 #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#define CFG_NAND_QUIET_TEST 1 /* * Internal Definitions |