diff options
| author | Stefano Babic <sbabic@denx.de> | 2020-05-10 13:03:56 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-05-10 13:03:56 +0200 |
| commit | b77d0292ca9f3ca69259dca7e2c5e193a403b289 (patch) | |
| tree | 0af352de3e405f839188aad7acaa9930d18afdd8 /include/configs/T102xRDB.h | |
| parent | 8142a97d541ef1473925b3677d6bf86bcddb69ac (diff) | |
| parent | c5c657644bc35fd6b3d6e5517698721e90646b8d (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'include/configs/T102xRDB.h')
| -rw-r--r-- | include/configs/T102xRDB.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 094795cc6d..c96d6e5f35 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -162,9 +163,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L3 Cache as L3 SRAM */ @@ -434,15 +432,20 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_PCA6408_BUS_NUM 1 #define I2C_PCA6408_ADDR 0x20 |