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authorJon Loeliger <jdl@freescale.com>2008-11-10 10:04:51 -0600
committerJon Loeliger <jdl@freescale.com>2008-11-10 10:04:51 -0600
commit33211469f7d7e2afacf103cc55790f734572f7a6 (patch)
tree7c374cde48fba08b52b4f83bdf00aae89d7f85a3 /include/configs/TASREG.h
parent1266df887781c779deaf6d05eea2ef90a470cb34 (diff)
parent1378174a1351c0285736863a665ab758fe8d5f71 (diff)
Merge commit 'wd/master'
Diffstat (limited to 'include/configs/TASREG.h')
-rw-r--r--include/configs/TASREG.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 18ffbfd72f..25f3a26f35 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -206,7 +206,7 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE 0xffc00000
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -257,15 +257,15 @@
*/
/* CS0 - AMD Flash, address 0xffc00000 */
-#define CONFIG_SYS_CSAR0 0xffc0
-#define CONFIG_SYS_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
+#define CONFIG_SYS_CS0_BASE 0xffc00000
+#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define CONFIG_SYS_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
+#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
-#define CONFIG_SYS_CSAR1 0xe000
-#define CONFIG_SYS_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
-#define CONFIG_SYS_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define CONFIG_SYS_CS1_BASE 0xe0000000
+#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
+#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration