diff options
| author | wdenk <wdenk> | 2003-06-05 19:27:42 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-06-05 19:27:42 +0000 |
| commit | 73a8b27c574f5ec1c8fdd9d8d065bb845d8743d3 (patch) | |
| tree | f409359364776e565b9484337a0620388041b456 /include/configs/TQM862L.h | |
| parent | 08eaea9c9fa4e8ea25325610c512cb90b6bea1dd (diff) | |
* Add support for RMU board
* Add support for TQM862L at 100/50 MHz
* Patch by Pantelis Antoniou, 02 Jun 2003:
major reconstruction of networking code;
add "ping" support (outgoing only!)
Diffstat (limited to 'include/configs/TQM862L.h')
| -rw-r--r-- | include/configs/TQM862L.h | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 653d0c79ae..1d0aea1fec 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -251,14 +251,15 @@ * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + * If this is a 80 MHz or 100 MHz CPU, + * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100) */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ +#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) #define CFG_PLPRCR \ ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) #else /* up to 50 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ +#endif /* CONFIG_80MHz | CONFIG_100MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -267,7 +268,7 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ +#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */ #define CFG_SCCR (/* SCCR_TBS | */ \ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ @@ -277,7 +278,7 @@ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ +#endif /* CONFIG_80MHz | CONFIG_100MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -346,8 +347,15 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ +#if defined(CONFIG_100MHz) +/* 100 MHz CPU - 50 MHz bus: + * 0x...926: 9 = OR_CSNT_SAM + OR_BI; 2 = OR_SCY_2_CLK; 6 = OR_TRLX + OR_EHTR + * ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +#elif defined(CONFIG_80MHz) +/* 80 MHz CPU - 40 MHz bus: + * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) #elif defined(CONFIG_66MHz) @@ -415,11 +423,14 @@ * -------------------------------------------- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + * 100 Mhz => 100.000.000 / Divider = 195 */ -#if defined(CONFIG_80MHz) +#if defined(CONFIG_100MHz) +#define CFG_MAMR_PTA 195 +#elif defined(CONFIG_80MHz) #define CFG_MAMR_PTA 156 #elif defined(CONFIG_66MHz) #define CFG_MAMR_PTA 129 |