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authorZhichun Hua <zhichun.hua@freescale.com>2015-06-29 15:50:42 +0800
committerYork Sun <yorksun@freescale.com>2015-07-20 11:44:40 -0700
commitdb14f11dfe348550d8c10c6609277488d9f500d6 (patch)
tree22d4e2a1e32e8f9d626a65173b994b49de54bb07 /include/configs/aria.h
parent21a257b9b3b29ddb1445fdafe12e05727080a198 (diff)
armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.
When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs/aria.h')
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