Coding style cleanup

1 files changed, 77 insertions, 77 deletions

diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index da3c29f191..6ccd8b9f38 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -30,13 +30,13 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_BAMBOO				1	/* Board is BAMBOO           */
-#define CONFIG_440_EP				1	/* Specific PPC440EP support */
+#define CONFIG_BAMBOO			1	/* Board is BAMBOO	     */
+#define CONFIG_440_EP			1	/* Specific PPC440EP support */
 
-#define CONFIG_4xx					1	/* ... PPC4xx family	*/
-#define CONFIG_BOARD_EARLY_INIT_F 	1   /* Call board_early_init_f	*/
-#undef	CFG_DRAM_TEST					/* disable - takes long time! */
-//#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
+#define CONFIG_4xx			1	/* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F	1   /* Call board_early_init_f	*/
+#undef	CFG_DRAM_TEST				/* disable - takes long time! */
+/*#define CONFIG_SYS_CLK_FREQ	66666666    /X* external freq to pll	*/
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
 /*-----------------------------------------------------------------------
@@ -64,24 +64,24 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	  0xf0000000		/* DCache */
+#define CFG_INIT_RAM_ADDR	0xf0000000		/* DCache */
 #define CFG_INIT_RAM_END	0x2000
-#define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
+#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data	*/
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
-#define CFG_KBYTES_SDRAM	( 128 * 1024)	/* 128MB                     */
-//#define CFG_SDRAM_BANKS     (2)
-#define CFG_SDRAM_BANKS     (1)
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc*/
+#define CFG_KBYTES_SDRAM	( 128 * 1024)	/* 128MB		     */
+/*#define CFG_SDRAM_BANKS	(2) */
+#define CFG_SDRAM_BANKS		(1)
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SERIAL_MULTI   1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI	1
 /*define this if you want console on UART1*/
 #undef CONFIG_UART1_CONSOLE
 
@@ -95,8 +95,8 @@
  * The DS1558 code assumes this condition
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/
+#define CFG_NVRAM_SIZE		(0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS1556	1			 /* DS1556 RTC		*/
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -109,9 +109,9 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	120000	    /* Timeout for Flash Write (in ms)	*/
 #else
-#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
-#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CFG_FLASH_CFI_AMD_RESET	1		/* AMD RESET for STM 29W320DB!  */
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+#define CFG_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
 
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
@@ -125,7 +125,7 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#undef CONFIG_SPD_EEPROM               /* Don't use SPD EEPROM for setup    */
+#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -139,9 +139,9 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#undef  CFG_ENV_IS_IN_NVRAM		    /*No NVRAM on board*/
+#undef	CFG_ENV_IS_IN_NVRAM		    /*No NVRAM on board*/
 #undef	CFG_ENV_IS_IN_FLASH		    /* ... not in flash		*/
-#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_IS_IN_EEPROM	1
 
 /* Define to allow the user to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -158,12 +158,12 @@
 #define CONFIG_BOOTCOMMAND	"bootm 0xfe000000"    /* autoboot command */
 #define CONFIG_BOOTDELAY	3		    /* disable autoboot */
 
-#define CONFIG_LOADS_ECHO		1	/* echo on for serial download	*/
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#define CONFIG_MII			1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI    1   /* required for netconsole  */
-#define CONFIG_PHY1_ADDR    3
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI	1	/* required for netconsole  */
+#define CONFIG_PHY1_ADDR	3
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
 #define CONFIG_NETMASK		255.255.255.0
@@ -196,49 +196,49 @@
 
 #ifdef CONFIG_440_EP
 	/* Need to define POST */
-#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL	| \
-			CFG_CMD_DATE	|   \
-			CFG_CMD_DHCP	|   \
-			CFG_CMD_DIAG	|   \
-			CFG_CMD_ECHO	|   \
-			CFG_CMD_EEPROM	|   \
-			CFG_CMD_ELF	|   \
-    /*      CFG_CMD_EXT2    |*/ \
-	/*		CFG_CMD_FAT		|*/	\
-			CFG_CMD_I2C	|	\
-	/*		CFG_CMD_IDE		|*/	\
-			CFG_CMD_IRQ	|	\
-    /*     	CFG_CMD_KGDB	|*/	\
-            		CFG_CMD_MII     |   \
-			CFG_CMD_PCI		|	\
-			CFG_CMD_PING	| 	\
-			CFG_CMD_REGINFO | 	\
-			CFG_CMD_SDRAM	|   \
-			CFG_CMD_FLASH   |   \
-	/*		CFG_CMD_SPI		|*/	\
-			CFG_CMD_USB	|	\
+#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL | \
+			CFG_CMD_DATE	| \
+			CFG_CMD_DHCP	| \
+			CFG_CMD_DIAG	| \
+			CFG_CMD_ECHO	| \
+			CFG_CMD_EEPROM	| \
+			CFG_CMD_ELF	| \
+		/*	CFG_CMD_EXT2	|*/ \
+		/*	CFG_CMD_FAT	|*/ \
+			CFG_CMD_I2C	| \
+		/*	CFG_CMD_IDE	|*/ \
+			CFG_CMD_IRQ	| \
+		/*	CFG_CMD_KGDB	|*/ \
+			CFG_CMD_MII	| \
+			CFG_CMD_PCI	| \
+			CFG_CMD_PING	| \
+			CFG_CMD_REGINFO | \
+			CFG_CMD_SDRAM	| \
+			CFG_CMD_FLASH	| \
+		/*	CFG_CMD_SPI	|*/ \
+			CFG_CMD_USB	| \
 			0 ) & ~CFG_CMD_IMLS)
 #else
-#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL	| \
-			CFG_CMD_DATE	|   \
-			CFG_CMD_DHCP	|   \
-			CFG_CMD_DIAG	|   \
-			CFG_CMD_ECHO	|   \
-			CFG_CMD_EEPROM	|   \
-			CFG_CMD_ELF	|   \
-    /*      CFG_CMD_EXT2    |*/ \
-	/*		CFG_CMD_FAT		|*/	\
-			CFG_CMD_I2C	|	\
-	/*		CFG_CMD_IDE		|*/	\
-			CFG_CMD_IRQ	|	\
-    /*     	CFG_CMD_KGDB	|*/	\
-            		CFG_CMD_MII     |   \
-			CFG_CMD_PCI		|	\
-			CFG_CMD_PING	| 	\
-			CFG_CMD_REGINFO | 	\
-			CFG_CMD_SDRAM	|   \
-			CFG_CMD_FLASH   |   \
-	/*		CFG_CMD_SPI		|*/	\
+#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL | \
+			CFG_CMD_DATE	| \
+			CFG_CMD_DHCP	| \
+			CFG_CMD_DIAG	| \
+			CFG_CMD_ECHO	| \
+			CFG_CMD_EEPROM	| \
+			CFG_CMD_ELF	| \
+		/*	CFG_CMD_EXT2	|*/ \
+		/*	CFG_CMD_FAT	|*/ \
+			CFG_CMD_I2C	| \
+		/*	CFG_CMD_IDE	|*/ \
+			CFG_CMD_IRQ	| \
+		/*	CFG_CMD_KGDB	|*/ \
+			CFG_CMD_MII	| \
+			CFG_CMD_PCI	| \
+			CFG_CMD_PING	| \
+			CFG_CMD_REGINFO | \
+			CFG_CMD_SDRAM	| \
+			CFG_CMD_FLASH	| \
+		/*	CFG_CMD_SPI	|*/ \
 			0 ) & ~CFG_CMD_IMLS)
 #endif
 
@@ -263,8 +263,8 @@
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 #define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		    1	/* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI          1   /* support kdi files */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI		1   /* support kdi files */
 
 #define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
@@ -273,18 +273,18 @@
  *-----------------------------------------------------------------------
  */
 /* General PCI */
-#define CONFIG_PCI			            /* include pci support	        */
-#undef  CONFIG_PCI_PNP			        /* do (not) pci plug-and-play         */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_PCI				/* include pci support		*/
+#undef	CONFIG_PCI_PNP				/* do (not) pci plug-and-play	*/
+#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM */
-#define CFG_PCI_SUBSYS_ID 0xcafe        /* Whatever */
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CFG_PCI_SUBSYS_ID 0xcafe	/* Whatever */
 
 /*
  * For booting Linux, the board info and command line data