diff options
| author | Manjunath Hadli <manjunath.hadli@ti.com> | 2011-10-07 23:33:32 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-10-27 21:56:35 +0200 |
| commit | 32317a5b7c8792f7186f84c5dbb48937a7168009 (patch) | |
| tree | 792b03a1d1633f922ed580e6a22aad5a25864581 /include/configs/davinci_dvevm.h | |
| parent | ba75a81a7ab8a9be21cfcf4a78306d831465913f (diff) | |
dm644X: revert cache disable patch
revert commit 913a39e9aa4d935948d41cd727d53f5878414a77 as the
disabling of cache need not be done explicitly. Subsequent
patches to new cache management framework has fixed it.
EMAC issue with cache coherency still exists when cahces are
enabled.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'include/configs/davinci_dvevm.h')
| -rw-r--r-- | include/configs/davinci_dvevm.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 88c6beeb9d..2507d79e4c 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -60,9 +60,6 @@ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SOC_DM644X -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_L2CACHE_OFF /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ |