diff options
| author | Chris Brandt <chris.brandt@renesas.com> | 2017-08-23 14:53:59 -0500 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-05-07 05:41:32 +0200 |
| commit | ba932bc846e8f44b7b61fcaac41e0be907d1303e (patch) | |
| tree | bc90d4a9923d4785063dfe2821db76b884158503 /include/configs/grpeach.h | |
| parent | 3529596442c9cf588b7b8a3e7573f0ff9d8ed350 (diff) | |
ARM: dts: renesas: Add RZ/A1 GR-Peach board
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .
Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'include/configs/grpeach.h')
| -rw-r--r-- | include/configs/grpeach.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h new file mode 100644 index 0000000000..01704d84c2 --- /dev/null +++ b/include/configs/grpeach.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Renesas GRPEACH board + * + * Copyright (C) 2017-2019 Renesas Electronics + */ + +#ifndef __GRPEACH_H +#define __GRPEACH_H + +/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* Serial Console */ +#define CONFIG_BAUDRATE 115200 + +/* Miscellaneous */ +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH +#define CONFIG_CMDLINE_TAG +#define CONFIG_ARCH_CPU_INIT + +/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) +#define CONFIG_SYS_LOAD_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET 0xc0000 + +/* Malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +/* Kernel Boot */ +#define CONFIG_BOOTARGS "ignore_loglevel" + +/* Network interface */ +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +#endif /* __GRPEACH_H */ |